| Design Name | ata_port_05a1 |
| Fitting Status | Successful |
| Software Version | I.27 |
| Device Used | XC95108-10-PC84 |
| Date | 9-19-2006, 1:35PM |
| Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
|---|---|---|---|---|
| 98/108 (91%) | 423/540 (79%) | 95/108 (88%) | 66/69 (96%) | 213/216 (99%) |
|
|
| Signal mapped onto global clock net (GCK1) | DIOWn |
| Signal mapped onto global clock net (GCK2) | /DIORn |
| Signal mapped onto global output enable net (GTS1) | REI |
| Signal mapped onto global output enable net (GSR) | /RESETn |
| Macrocells in high performance mode (MCHP) | 98 |
| Macrocells in low power mode (MCLP) | 0 |
| Total macrocells used (MC) | 98 |