cpldfit: version I.27 Xilinx Inc.
Fitter Report
Design Name: ata_port_05a1 Date: 9-19-2006, 1:35PM
Device Used: XC95108-10-PC84
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
98 /108 ( 91%) 423 /540 ( 78%) 213/216 ( 99%) 95 /108 ( 88%) 58 /69 ( 84%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 17/18 36/36* 36 72/90 9/12
FB2 17/18 36/36* 36 72/90 9/12
FB3 17/18 35/36 38 71/90 9/12
FB4 16/18 35/36 35 78/90 9/11
FB5 17/18 35/36 35 72/90 10/11
FB6 14/18 36/36* 36 58/90 8/11
----- ----- ----- -----
98/108 213/216 423/540 54/69
* - Resource is exhausted
** Global Control Resources **
Signal 'DIOWn' mapped onto global clock net GCK1.
The complement of 'DIORn' mapped onto global clock net GCK2.
Signal 'REI' mapped onto global output enable net GTS1.
The complement of 'RESETn' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 8 8 | I/O : 62 63
Output : 6 6 | GCK/IO : 2 3
Bidirectional : 48 48 | GTS/IO : 1 2
GCK : 2 2 | GSR/IO : 1 1
GTS : 1 1 |
GSR : 1 1 |
---- ----
Total 66 66
** Power Data **
There are 98 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:888 - Signal DD<7> has been buffered in an attempt to find a fit.
************************* Summary of Mapped Logic ************************
** 54 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DD<4> 5 9 FB1_2 1 I/O I/O STD SLOW RESET
PORTE<0> 5 16 FB1_3 2 I/O I/O STD SLOW RESET
PORTE<1> 5 16 FB1_5 3 I/O I/O STD SLOW RESET
PORTB<0> 5 16 FB1_6 4 I/O I/O STD SLOW RESET
PORTB<1> 5 16 FB1_8 5 I/O I/O STD SLOW RESET
PORTA<0> 5 16 FB1_9 6 I/O I/O STD SLOW RESET
PORTD<0> 5 16 FB1_11 7 I/O I/O STD SLOW RESET
PORTC<0> 5 16 FB1_15 11 I/O I/O STD SLOW RESET
DH0n 2 9 FB1_17 13 I/O O STD SLOW SET
DD<3> 5 9 FB2_2 71 I/O I/O STD SLOW RESET
PORTE<2> 5 16 FB2_3 72 I/O I/O STD SLOW RESET
PORTE<3> 5 16 FB2_6 75 I/O I/O STD SLOW RESET
PORTB<2> 5 16 FB2_11 79 I/O I/O STD SLOW RESET
PORTB<3> 5 16 FB2_12 80 I/O I/O STD SLOW RESET
PORTA<2> 5 16 FB2_14 81 I/O I/O STD SLOW RESET
PORTD<2> 5 16 FB2_15 82 I/O I/O STD SLOW RESET
PORTC<2> 5 16 FB2_16 83 I/O I/O STD SLOW RESET
DH2n 2 9 FB2_17 84 I/O O STD SLOW SET
DD<1> 5 9 FB3_2 14 I/O I/O STD SLOW RESET
PORTE<4> 5 16 FB3_3 15 I/O I/O STD SLOW RESET
PORTE<5> 5 16 FB3_5 17 I/O I/O STD SLOW RESET
PORTB<4> 5 16 FB3_6 18 I/O I/O STD SLOW RESET
PORTB<5> 5 16 FB3_8 19 I/O I/O STD SLOW RESET
PORTA<4> 5 16 FB3_9 20 I/O I/O STD SLOW RESET
PORTD<4> 5 16 FB3_11 21 I/O I/O STD SLOW RESET
PORTC<4> 5 16 FB3_12 23 I/O I/O STD SLOW RESET
DD<7> 1 4 FB3_14 24 I/O I/O STD SLOW
REO 10 13 FB4_2 57 I/O O STD SLOW
DD<2> 5 9 FB4_3 58 I/O I/O STD SLOW RESET
PORTE<6> 5 16 FB4_5 61 I/O I/O STD SLOW RESET
PORTE<7> 5 16 FB4_6 62 I/O I/O STD SLOW RESET
PORTB<6> 5 16 FB4_8 63 I/O I/O STD SLOW RESET
PORTB<7> 5 16 FB4_9 65 I/O I/O STD SLOW RESET
PORTA<6> 5 16 FB4_11 66 I/O I/O STD SLOW RESET
PORTD<6> 5 16 FB4_12 67 I/O I/O STD SLOW RESET
PORTC<6> 5 16 FB4_14 68 I/O I/O STD SLOW RESET
DD<6> 5 9 FB5_2 32 I/O I/O STD SLOW RESET
PORTA<1> 5 16 FB5_3 33 I/O I/O STD SLOW RESET
PORTA<3> 5 16 FB5_5 34 I/O I/O STD SLOW RESET
PORTA<5> 5 16 FB5_6 35 I/O I/O STD SLOW RESET
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
PORTD<1> 5 16 FB5_8 36 I/O I/O STD SLOW RESET
PORTD<3> 5 16 FB5_9 37 I/O I/O STD SLOW RESET
PORTC<1> 5 16 FB5_11 39 I/O I/O STD SLOW RESET
PORTC<3> 5 16 FB5_12 40 I/O I/O STD SLOW RESET
DH1n 2 9 FB5_14 41 I/O O STD SLOW SET
DH3n 2 9 FB5_15 43 I/O O STD SLOW SET
DD<0> 5 9 FB6_2 45 I/O I/O STD SLOW RESET
DD<5> 5 9 FB6_3 46 I/O I/O STD SLOW RESET
PORTA<7> 5 16 FB6_5 47 I/O I/O STD SLOW RESET
PORTD<5> 5 16 FB6_6 48 I/O I/O STD SLOW RESET
PORTD<7> 5 16 FB6_8 50 I/O I/O STD SLOW RESET
PORTC<5> 5 16 FB6_9 51 I/O I/O STD SLOW RESET
PORTC<7> 5 16 FB6_11 52 I/O I/O STD SLOW RESET
SELECTEDn 2 2 FB6_12 53 I/O O STD SLOW
** 44 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
DD<7>_BUFR_1_ 2 6 FB1_4 STD RESET
XLXI_87/DIR<0> 4 15 FB1_7 STD RESET
XLXI_86/DIR<0> 4 15 FB1_10 STD RESET
XLXI_85/DIR<0> 4 15 FB1_12 STD RESET
XLXI_82/DIR<1> 4 15 FB1_13 STD RESET
XLXI_82/DIR<0> 4 15 FB1_14 STD RESET
XLXI_80/DIR<1> 4 15 FB1_16 STD RESET
XLXI_80/DIR<0> 4 15 FB1_18 STD RESET
DD<7>_BUFR_0_ 2 6 FB2_4 STD RESET
XLXI_87/DIR<2> 4 15 FB2_5 STD RESET
XLXI_86/DIR<2> 4 15 FB2_7 STD RESET
XLXI_85/DIR<2> 4 15 FB2_8 STD RESET
XLXI_82/DIR<3> 4 15 FB2_9 STD RESET
XLXI_82/DIR<2> 4 15 FB2_10 STD RESET
XLXI_80/DIR<3> 4 15 FB2_13 STD RESET
XLXI_80/DIR<2> 4 15 FB2_18 STD RESET
XLXI_178/XLXN_43 2 9 FB3_4 STD RESET
XLXI_87/DIR<4> 4 15 FB3_7 STD RESET
XLXI_86/DIR<4> 4 15 FB3_10 STD RESET
XLXI_85/DIR<4> 4 15 FB3_13 STD RESET
XLXI_82/DIR<5> 4 15 FB3_15 STD RESET
XLXI_82/DIR<4> 4 15 FB3_16 STD RESET
XLXI_80/DIR<5> 4 15 FB3_17 STD RESET
XLXI_80/DIR<4> 4 15 FB3_18 STD RESET
XLXI_87/DIR<6> 4 15 FB4_7 STD RESET
XLXI_86/DIR<6> 4 15 FB4_10 STD RESET
XLXI_85/DIR<6> 4 15 FB4_13 STD RESET
XLXI_82/DIR<7> 4 15 FB4_15 STD RESET
XLXI_82/DIR<6> 4 15 FB4_16 STD RESET
XLXI_80/DIR<7> 4 15 FB4_17 STD RESET
XLXI_80/DIR<6> 4 15 FB4_18 STD RESET
XLXI_87/DIR<3> 4 15 FB5_4 STD RESET
XLXI_87/DIR<1> 4 15 FB5_7 STD RESET
XLXI_86/DIR<3> 4 15 FB5_10 STD RESET
XLXI_86/DIR<1> 4 15 FB5_13 STD RESET
XLXI_85/DIR<5> 4 15 FB5_16 STD RESET
XLXI_85/DIR<3> 4 15 FB5_17 STD RESET
XLXI_85/DIR<1> 4 15 FB5_18 STD RESET
DD<7>_BUFR_2_ 1 5 FB6_13 STD RESET
XLXI_87/DIR<7> 4 15 FB6_14 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_87/DIR<5> 4 15 FB6_15 STD RESET
XLXI_86/DIR<7> 4 15 FB6_16 STD RESET
XLXI_86/DIR<5> 4 15 FB6_17 STD RESET
XLXI_85/DIR<7> 4 15 FB6_18 STD RESET
** 12 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
DIOWn FB1_12 9~ GCK/I/O GCK
DIORn FB1_14 10~ GCK/I/O GCK/I
RESETn FB2_5 74~ GSR/I/O GSR
REI FB2_8 76~ GTS/I/O GTS
DA2 FB3_16 26 I/O I
CSEL FB3_17 31 I/O I
CS1n FB4_15 69 I/O I
DA1 FB4_17 70 I/O I
DA0 FB5_17 44 I/O I
CS0n FB6_14 54 I/O I
DMARQ FB6_15 55 I/O I
DMACKn FB6_17 56 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 36/0
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
DD<4> 5 0 0 0 FB1_2 1 I/O I/O
PORTE<0> 5 0 0 0 FB1_3 2 I/O I/O
DD<7>_BUFR_1_ 2 0 0 3 FB1_4 (b) (b)
PORTE<1> 5 0 0 0 FB1_5 3 I/O I/O
PORTB<0> 5 0 0 0 FB1_6 4 I/O I/O
XLXI_87/DIR<0> 4 0 0 1 FB1_7 (b) (b)
PORTB<1> 5 0 0 0 FB1_8 5 I/O I/O
PORTA<0> 5 0 0 0 FB1_9 6 I/O I/O
XLXI_86/DIR<0> 4 0 0 1 FB1_10 (b) (b)
PORTD<0> 5 0 0 0 FB1_11 7 I/O I/O
XLXI_85/DIR<0> 4 0 0 1 FB1_12 9 GCK/I/O GCK
XLXI_82/DIR<1> 4 0 0 1 FB1_13 (b) (b)
XLXI_82/DIR<0> 4 0 0 1 FB1_14 10 GCK/I/O GCK/I
PORTC<0> 5 0 0 0 FB1_15 11 I/O I/O
XLXI_80/DIR<1> 4 0 0 1 FB1_16 12 GCK/I/O (b)
DH0n 2 0 0 3 FB1_17 13 I/O O
XLXI_80/DIR<0> 4 0 0 1 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 13: PORTE<7>.PIN 25: XLXI_80/DIR<0>.LFBK
2: DA1 14: DD<0>.PIN 26: XLXI_80/DIR<1>.LFBK
3: DA2 15: DD<1>.PIN 27: XLXI_82/DAT<0>.LFBK
4: DH1n 16: CSEL 28: XLXI_82/DAT<1>.LFBK
5: DH2n 17: DMARQ 29: XLXI_82/DIR<0>.LFBK
6: DH3n 18: CS0n 30: XLXI_82/DIR<1>.LFBK
7: PORTA<4>.PIN 19: XLXI_178/XLXN_43 31: XLXI_85/DAT<0>.LFBK
8: PORTB<4>.PIN 20: XLXI_178/XLXN_447.LFBK 32: XLXI_85/DIR<0>.LFBK
9: PORTC<4>.PIN 21: DMACKn 33: XLXI_86/DAT<0>.LFBK
10: PORTD<4>.PIN 22: CS1n 34: XLXI_86/DIR<0>.LFBK
11: PORTD<7>.PIN 23: XLXI_80/DAT<0>.LFBK 35: XLXI_87/DAT<0>.LFBK
12: PORTE<4>.PIN 24: XLXI_80/DAT<1>.LFBK 36: XLXI_87/DIR<0>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<4> ...XXXXXXX.X.......X.................... 9 9
PORTE<0> XXXXXX.......X.XXXXXXXX.X............... 16 16
DD<7>_BUFR_1_ ...XXX....X.X......X.................... 6 6
PORTE<1> XXXXXX........XXXXXXXX.X.X.............. 16 16
PORTB<0> XXXXXX.......X.XXXXXXX....X.X........... 16 16
XLXI_87/DIR<0> XXXXXX.......X.XXXXXXX.............X.... 15 15
PORTB<1> XXXXXX........XXXXXXXX.....X.X.......... 16 16
PORTA<0> XXXXXX.......X.XXXXXXX........XX........ 16 16
XLXI_86/DIR<0> XXXXXX.......X.XXXXXXX...........X...... 15 15
PORTD<0> XXXXXX.......X.XXXXXXX..........XX...... 16 16
XLXI_85/DIR<0> XXXXXX.......X.XXXXXXX.........X........ 15 15
XLXI_82/DIR<1> XXXXXX........XXXXXXXX.......X.......... 15 15
XLXI_82/DIR<0> XXXXXX.......X.XXXXXXX......X........... 15 15
PORTC<0> XXXXXX.......X.XXXXXXX............XX.... 16 16
XLXI_80/DIR<1> XXXXXX........XXXXXXXX...X.............. 15 15
DH0n XXX..........X..XX.XXX.................. 9 9
XLXI_80/DIR<0> XXXXXX.......X.XXXXXXX..X............... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 36/0
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
DD<3> 5 0 0 0 FB2_2 71 I/O I/O
PORTE<2> 5 0 0 0 FB2_3 72 I/O I/O
DD<7>_BUFR_0_ 2 0 0 3 FB2_4 (b) (b)
XLXI_87/DIR<2> 4 0 0 1 FB2_5 74 GSR/I/O GSR
PORTE<3> 5 0 0 0 FB2_6 75 I/O I/O
XLXI_86/DIR<2> 4 0 0 1 FB2_7 (b) (b)
XLXI_85/DIR<2> 4 0 0 1 FB2_8 76 GTS/I/O GTS
XLXI_82/DIR<3> 4 0 0 1 FB2_9 77 GTS/I/O (b)
XLXI_82/DIR<2> 4 0 0 1 FB2_10 (b) (b)
PORTB<2> 5 0 0 0 FB2_11 79 I/O I/O
PORTB<3> 5 0 0 0 FB2_12 80 I/O I/O
XLXI_80/DIR<3> 4 0 0 1 FB2_13 (b) (b)
PORTA<2> 5 0 0 0 FB2_14 81 I/O I/O
PORTD<2> 5 0 0 0 FB2_15 82 I/O I/O
PORTC<2> 5 0 0 0 FB2_16 83 I/O I/O
DH2n 2 0 0 3 FB2_17 84 I/O O
XLXI_80/DIR<2> 4 0 0 1 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 13: PORTE<3>.PIN 25: XLXI_80/DIR<2>.LFBK
2: DA1 14: DD<2>.PIN 26: XLXI_80/DIR<3>.LFBK
3: DA2 15: DD<3>.PIN 27: XLXI_82/DAT<2>.LFBK
4: DH0n 16: CSEL 28: XLXI_82/DAT<3>.LFBK
5: DH1n 17: DMARQ 29: XLXI_82/DIR<2>.LFBK
6: DH3n 18: CS0n 30: XLXI_82/DIR<3>.LFBK
7: PORTA<3>.PIN 19: XLXI_178/XLXN_43 31: XLXI_85/DAT<2>.LFBK
8: PORTA<7>.PIN 20: XLXI_178/XLXN_449.LFBK 32: XLXI_85/DIR<2>.LFBK
9: PORTB<3>.PIN 21: DMACKn 33: XLXI_86/DAT<2>.LFBK
10: PORTC<3>.PIN 22: CS1n 34: XLXI_86/DIR<2>.LFBK
11: PORTC<7>.PIN 23: XLXI_80/DAT<2>.LFBK 35: XLXI_87/DAT<2>.LFBK
12: PORTD<3>.PIN 24: XLXI_80/DAT<3>.LFBK 36: XLXI_87/DIR<2>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<3> ...XXXX.XX.XX......X.................... 9 9
PORTE<2> XXXXXX.......X.XXXXXXXX.X............... 16 16
DD<7>_BUFR_0_ ...XXX.X..X........X.................... 6 6
XLXI_87/DIR<2> XXXXXX.......X.XXXXXXX.............X.... 15 15
PORTE<3> XXXXXX........XXXXXXXX.X.X.............. 16 16
XLXI_86/DIR<2> XXXXXX.......X.XXXXXXX...........X...... 15 15
XLXI_85/DIR<2> XXXXXX.......X.XXXXXXX.........X........ 15 15
XLXI_82/DIR<3> XXXXXX........XXXXXXXX.......X.......... 15 15
XLXI_82/DIR<2> XXXXXX.......X.XXXXXXX......X........... 15 15
PORTB<2> XXXXXX.......X.XXXXXXX....X.X........... 16 16
PORTB<3> XXXXXX........XXXXXXXX.....X.X.......... 16 16
XLXI_80/DIR<3> XXXXXX........XXXXXXXX...X.............. 15 15
PORTA<2> XXXXXX.......X.XXXXXXX........XX........ 16 16
PORTD<2> XXXXXX.......X.XXXXXXX..........XX...... 16 16
PORTC<2> XXXXXX.......X.XXXXXXX............XX.... 16 16
DH2n XXX..........X..XX.XXX.................. 9 9
XLXI_80/DIR<2> XXXXXX.......X.XXXXXXX..X............... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 38
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
DD<1> 5 0 0 0 FB3_2 14 I/O I/O
PORTE<4> 5 0 0 0 FB3_3 15 I/O I/O
XLXI_178/XLXN_43 2 0 0 3 FB3_4 (b) (b)
PORTE<5> 5 0 0 0 FB3_5 17 I/O I/O
PORTB<4> 5 0 0 0 FB3_6 18 I/O I/O
XLXI_87/DIR<4> 4 0 0 1 FB3_7 (b) (b)
PORTB<5> 5 0 0 0 FB3_8 19 I/O I/O
PORTA<4> 5 0 0 0 FB3_9 20 I/O I/O
XLXI_86/DIR<4> 4 0 0 1 FB3_10 (b) (b)
PORTD<4> 5 0 0 0 FB3_11 21 I/O I/O
PORTC<4> 5 0 0 0 FB3_12 23 I/O I/O
XLXI_85/DIR<4> 4 0 0 1 FB3_13 (b) (b)
DD<7> 1 0 0 4 FB3_14 24 I/O I/O
XLXI_82/DIR<5> 4 0 0 1 FB3_15 25 I/O (b)
XLXI_82/DIR<4> 4 0 0 1 FB3_16 26 I/O I
XLXI_80/DIR<5> 4 0 0 1 FB3_17 31 I/O I
XLXI_80/DIR<4> 4 0 0 1 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 14: PORTC<1>.PIN 27: XLXI_80/DIR<4>.LFBK
2: DA1 15: PORTD<1>.PIN 28: XLXI_80/DIR<5>.LFBK
3: DA2 16: PORTE<1>.PIN 29: XLXI_82/DAT<4>.LFBK
4: DD<7>_BUFR 17: DD<4>.PIN 30: XLXI_82/DAT<5>.LFBK
5: DD<7>_BUFR_0_ 18: DD<5>.PIN 31: XLXI_82/DIR<4>.LFBK
6: DD<7>_BUFR_1_ 19: CSEL 32: XLXI_82/DIR<5>.LFBK
7: DD<7>_BUFR_2_ 20: DMARQ 33: XLXI_85/DAT<4>.LFBK
8: DH0n 21: CS0n 34: XLXI_85/DIR<4>.LFBK
9: DH1n 22: XLXI_178/XLXN_43.LFBK 35: XLXI_86/DAT<4>.LFBK
10: DH2n 23: DMACKn 36: XLXI_86/DIR<4>.LFBK
11: DH3n 24: CS1n 37: XLXI_87/DAT<4>.LFBK
12: PORTA<1>.PIN 25: XLXI_80/DAT<4>.LFBK 38: XLXI_87/DIR<4>.LFBK
13: PORTB<1>.PIN 26: XLXI_80/DAT<5>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<1> .......XXXXXXXXX........................ 9 9
PORTE<4> XXX....XXXX.....X.XXXXXXX.X............. 16 16
XLXI_178/XLXN_43 XXX.............X..XXXXX................ 9 9
PORTE<5> XXX....XXXX......XXXXXXX.X.X............ 16 16
PORTB<4> XXX....XXXX.....X.XXXXXX....X.X......... 16 16
XLXI_87/DIR<4> XXX....XXXX.....X.XXXXXX.............X.. 15 15
PORTB<5> XXX....XXXX......XXXXXXX.....X.X........ 16 16
PORTA<4> XXX....XXXX.....X.XXXXXX........XX...... 16 16
XLXI_86/DIR<4> XXX....XXXX.....X.XXXXXX...........X.... 15 15
PORTD<4> XXX....XXXX.....X.XXXXXX..........XX.... 16 16
PORTC<4> XXX....XXXX.....X.XXXXXX............XX.. 16 16
XLXI_85/DIR<4> XXX....XXXX.....X.XXXXXX.........X...... 15 15
DD<7> ...X@@@................................. 4 1
XLXI_82/DIR<5> XXX....XXXX......XXXXXXX.......X........ 15 15
XLXI_82/DIR<4> XXX....XXXX.....X.XXXXXX......X......... 15 15
XLXI_80/DIR<5> XXX....XXXX......XXXXXXX...X............ 15 15
XLXI_80/DIR<4> XXX....XXXX.....X.XXXXXX..X............. 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB4_1 (b) (b)
REO 10 5<- 0 0 FB4_2 57 I/O O
DD<2> 5 0 0 0 FB4_3 58 I/O I/O
(unused) 0 0 0 5 FB4_4 (b)
PORTE<6> 5 0 0 0 FB4_5 61 I/O I/O
PORTE<7> 5 0 0 0 FB4_6 62 I/O I/O
XLXI_87/DIR<6> 4 0 0 1 FB4_7 (b) (b)
PORTB<6> 5 0 0 0 FB4_8 63 I/O I/O
PORTB<7> 5 0 0 0 FB4_9 65 I/O I/O
XLXI_86/DIR<6> 4 0 0 1 FB4_10 (b) (b)
PORTA<6> 5 0 0 0 FB4_11 66 I/O I/O
PORTD<6> 5 0 0 0 FB4_12 67 I/O I/O
XLXI_85/DIR<6> 4 0 0 1 FB4_13 (b) (b)
PORTC<6> 5 0 0 0 FB4_14 68 I/O I/O
XLXI_82/DIR<7> 4 0 0 1 FB4_15 69 I/O I
XLXI_82/DIR<6> 4 0 0 1 FB4_16 (b) (b)
XLXI_80/DIR<7> 4 0 0 1 FB4_17 70 I/O I
XLXI_80/DIR<6> 4 0 0 1 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 13: DD<6>.PIN 25: XLXI_80/DIR<7>.LFBK
2: DA1 14: DD<7>.PIN 26: XLXI_82/DAT<6>.LFBK
3: DA2 15: DIORn 27: XLXI_82/DAT<7>.LFBK
4: DH0n 16: CSEL 28: XLXI_82/DIR<6>.LFBK
5: DH1n 17: DMARQ 29: XLXI_82/DIR<7>.LFBK
6: DH2n 18: CS0n 30: XLXI_85/DAT<6>.LFBK
7: DH3n 19: XLXI_178/XLXN_43 31: XLXI_85/DIR<6>.LFBK
8: PORTA<2>.PIN 20: DMACKn 32: XLXI_86/DAT<6>.LFBK
9: PORTB<2>.PIN 21: CS1n 33: XLXI_86/DIR<6>.LFBK
10: PORTC<2>.PIN 22: XLXI_80/DAT<6>.LFBK 34: XLXI_87/DAT<6>.LFBK
11: PORTD<2>.PIN 23: XLXI_80/DAT<7>.LFBK 35: XLXI_87/DIR<6>.LFBK
12: PORTE<2>.PIN 24: XLXI_80/DIR<6>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
REO XXX.XXX.......XXXXXXX................... 13 13
DD<2> ...XXXXXXXXX............................ 9 9
PORTE<6> XXXXXXX.....X..XXXXXXX.X................ 16 16
PORTE<7> XXXXXXX......X.XXXXXX.X.X............... 16 16
XLXI_87/DIR<6> XXXXXXX.....X..XXXXXX.............X..... 15 15
PORTB<6> XXXXXXX.....X..XXXXXX....X.X............ 16 16
PORTB<7> XXXXXXX......X.XXXXXX.....X.X........... 16 16
XLXI_86/DIR<6> XXXXXXX.....X..XXXXXX...........X....... 15 15
PORTA<6> XXXXXXX.....X..XXXXXX........XX......... 16 16
PORTD<6> XXXXXXX.....X..XXXXXX..........XX....... 16 16
XLXI_85/DIR<6> XXXXXXX.....X..XXXXXX.........X......... 15 15
PORTC<6> XXXXXXX.....X..XXXXXX............XX..... 16 16
XLXI_82/DIR<7> XXXXXXX......X.XXXXXX.......X........... 15 15
XLXI_82/DIR<6> XXXXXXX.....X..XXXXXX......X............ 15 15
XLXI_80/DIR<7> XXXXXXX......X.XXXXXX...X............... 15 15
XLXI_80/DIR<6> XXXXXXX.....X..XXXXXX..X................ 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
DD<6> 5 0 0 0 FB5_2 32 I/O I/O
PORTA<1> 5 0 0 0 FB5_3 33 I/O I/O
XLXI_87/DIR<3> 4 0 0 1 FB5_4 (b) (b)
PORTA<3> 5 0 0 0 FB5_5 34 I/O I/O
PORTA<5> 5 0 0 0 FB5_6 35 I/O I/O
XLXI_87/DIR<1> 4 0 0 1 FB5_7 (b) (b)
PORTD<1> 5 0 0 0 FB5_8 36 I/O I/O
PORTD<3> 5 0 0 0 FB5_9 37 I/O I/O
XLXI_86/DIR<3> 4 0 0 1 FB5_10 (b) (b)
PORTC<1> 5 0 0 0 FB5_11 39 I/O I/O
PORTC<3> 5 0 0 0 FB5_12 40 I/O I/O
XLXI_86/DIR<1> 4 0 0 1 FB5_13 (b) (b)
DH1n 2 0 0 3 FB5_14 41 I/O O
DH3n 2 0 0 3 FB5_15 43 I/O O
XLXI_85/DIR<5> 4 0 0 1 FB5_16 (b) (b)
XLXI_85/DIR<3> 4 0 0 1 FB5_17 44 I/O I
XLXI_85/DIR<1> 4 0 0 1 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 13: DD<5>.PIN 25: XLXI_85/DIR<1>.LFBK
2: DA1 14: CSEL 26: XLXI_85/DIR<3>.LFBK
3: DA2 15: DMARQ 27: XLXI_85/DIR<5>.LFBK
4: DH0n 16: CS0n 28: XLXI_86/DAT<1>.LFBK
5: DH2n 17: XLXI_178/XLXN_43 29: XLXI_86/DAT<3>.LFBK
6: PORTA<6>.PIN 18: XLXI_178/XLXN_448.LFBK 30: XLXI_86/DIR<1>.LFBK
7: PORTB<6>.PIN 19: XLXI_178/XLXN_450.LFBK 31: XLXI_86/DIR<3>.LFBK
8: PORTC<6>.PIN 20: DMACKn 32: XLXI_87/DAT<1>.LFBK
9: PORTD<6>.PIN 21: CS1n 33: XLXI_87/DAT<3>.LFBK
10: PORTE<6>.PIN 22: XLXI_85/DAT<1>.LFBK 34: XLXI_87/DIR<1>.LFBK
11: DD<1>.PIN 23: XLXI_85/DAT<3>.LFBK 35: XLXI_87/DIR<3>.LFBK
12: DD<3>.PIN 24: XLXI_85/DAT<5>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<6> ...XXXXXXX.......XX..................... 9 9
PORTA<1> XXXXX.....X..XXXXXXXXX..X............... 16 16
XLXI_87/DIR<3> XXXXX......X.XXXXXXXX.............X..... 15 15
PORTA<3> XXXXX......X.XXXXXXXX.X..X.............. 16 16
PORTA<5> XXXXX.......XXXXXXXXX..X..X............. 16 16
XLXI_87/DIR<1> XXXXX.....X..XXXXXXXX............X...... 15 15
PORTD<1> XXXXX.....X..XXXXXXXX......X.X.......... 16 16
PORTD<3> XXXXX......X.XXXXXXXX.......X.X......... 16 16
XLXI_86/DIR<3> XXXXX......X.XXXXXXXX.........X......... 15 15
PORTC<1> XXXXX.....X..XXXXXXXX..........X.X...... 16 16
PORTC<3> XXXXX......X.XXXXXXXX...........X.X..... 16 16
XLXI_86/DIR<1> XXXXX.....X..XXXXXXXX........X.......... 15 15
DH1n XXX.......X...XX.X.XX................... 9 9
DH3n XXX........X..XX..XXX................... 9 9
XLXI_85/DIR<5> XXXXX.......XXXXXXXXX.....X............. 15 15
XLXI_85/DIR<3> XXXXX......X.XXXXXXXX....X.............. 15 15
XLXI_85/DIR<1> XXXXX.....X..XXXXXXXX...X............... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 36/0
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
DD<0> 5 0 0 0 FB6_2 45 I/O I/O
DD<5> 5 0 0 0 FB6_3 46 I/O I/O
(unused) 0 0 0 5 FB6_4 (b)
PORTA<7> 5 0 0 0 FB6_5 47 I/O I/O
PORTD<5> 5 0 0 0 FB6_6 48 I/O I/O
(unused) 0 0 0 5 FB6_7 (b)
PORTD<7> 5 0 0 0 FB6_8 50 I/O I/O
PORTC<5> 5 0 0 0 FB6_9 51 I/O I/O
(unused) 0 0 0 5 FB6_10 (b)
PORTC<7> 5 0 0 0 FB6_11 52 I/O I/O
SELECTEDn 2 0 0 3 FB6_12 53 I/O O
DD<7>_BUFR_2_ 1 0 0 4 FB6_13 (b) (b)
XLXI_87/DIR<7> 4 0 0 1 FB6_14 54 I/O I
XLXI_87/DIR<5> 4 0 0 1 FB6_15 55 I/O I
XLXI_86/DIR<7> 4 0 0 1 FB6_16 (b) (b)
XLXI_86/DIR<5> 4 0 0 1 FB6_17 56 I/O I
XLXI_85/DIR<7> 4 0 0 1 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 13: PORTC<0>.PIN 25: DMACKn
2: DA1 14: PORTC<5>.PIN 26: CS1n
3: DA2 15: PORTD<0>.PIN 27: XLXI_85/DAT<7>.LFBK
4: DH0n 16: PORTD<5>.PIN 28: XLXI_85/DIR<7>.LFBK
5: DH1n 17: PORTE<0>.PIN 29: XLXI_86/DAT<5>.LFBK
6: DH2n 18: PORTE<5>.PIN 30: XLXI_86/DAT<7>.LFBK
7: DH3n 19: DD<5>.PIN 31: XLXI_86/DIR<5>.LFBK
8: PORTA<0>.PIN 20: DD<7>.PIN 32: XLXI_86/DIR<7>.LFBK
9: PORTA<5>.PIN 21: CSEL 33: XLXI_87/DAT<5>.LFBK
10: PORTB<0>.PIN 22: DMARQ 34: XLXI_87/DAT<7>.LFBK
11: PORTB<5>.PIN 23: CS0n 35: XLXI_87/DIR<5>.LFBK
12: PORTB<7>.PIN 24: XLXI_178/XLXN_43 36: XLXI_87/DIR<7>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<0> ...XXXXX.X..X.X.X....................... 9 9
DD<5> ...XXXX.X.X..X.X.X...................... 9 9
PORTA<7> XXXXXXX............XXXXXXXXX............ 16 16
PORTD<5> XXXXXXX...........X.XXXXXX..X.X......... 16 16
PORTD<7> XXXXXXX............XXXXXXX...X.X........ 16 16
PORTC<5> XXXXXXX...........X.XXXXXX......X.X..... 16 16
PORTC<7> XXXXXXX............XXXXXXX.......X.X.... 16 16
SELECTEDn ....................X..X................ 2 2
DD<7>_BUFR_2_ ...XXXX....X............................ 5 5
XLXI_87/DIR<7> XXXXXXX............XXXXXXX.........X.... 15 15
XLXI_87/DIR<5> XXXXXXX...........X.XXXXXX........X..... 15 15
XLXI_86/DIR<7> XXXXXXX............XXXXXXX.....X........ 15 15
XLXI_86/DIR<5> XXXXXXX...........X.XXXXXX....X......... 15 15
XLXI_85/DIR<7> XXXXXXX............XXXXXXX.X............ 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FDCPE_DD0: FDCPE port map (DD_I(0),DD(0),NOT DIORn,'0','0');
DD(0) <= ((PORTA(0).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(0).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(0).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(0).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(0).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD1: FDCPE port map (DD_I(1),DD(1),NOT DIORn,'0','0');
DD(1) <= ((PORTA(1).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(1).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(1).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(1).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(1).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD2: FDCPE port map (DD_I(2),DD(2),NOT DIORn,'0','0');
DD(2) <= ((PORTA(2).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(2).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(2).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(2).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(2).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD3: FDCPE port map (DD_I(3),DD(3),NOT DIORn,'0','0');
DD(3) <= ((PORTA(3).PIN AND NOT DH0n AND DH1n AND DH3n AND
XLXI_178/XLXN_449.LFBK)
OR (PORTE(3).PIN AND NOT DH0n AND DH1n AND DH3n AND
NOT XLXI_178/XLXN_449.LFBK)
OR (PORTC(3).PIN AND NOT DH0n AND NOT DH1n AND DH3n AND
XLXI_178/XLXN_449.LFBK)
OR (PORTB(3).PIN AND DH0n AND NOT DH1n AND DH3n AND
XLXI_178/XLXN_449.LFBK)
OR (PORTD(3).PIN AND DH0n AND DH1n AND DH3n AND
NOT XLXI_178/XLXN_449.LFBK));
FDCPE_DD4: FDCPE port map (DD_I(4),DD(4),NOT DIORn,'0','0');
DD(4) <= ((PORTA(4).PIN AND DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTE(4).PIN AND DH1n AND NOT DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTC(4).PIN AND NOT DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTB(4).PIN AND NOT DH1n AND DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK)
OR (PORTD(4).PIN AND DH1n AND NOT DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK));
FDCPE_DD5: FDCPE port map (DD_I(5),DD(5),NOT DIORn,'0','0');
DD(5) <= ((PORTA(5).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(5).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(5).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD6: FDCPE port map (DD_I(6),DD(6),NOT DIORn,'0','0');
DD(6) <= ((PORTA(6).PIN AND NOT DH0n AND DH2n AND
XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK)
OR (PORTE(6).PIN AND NOT DH0n AND NOT DH2n AND
XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK)
OR (PORTC(6).PIN AND NOT DH0n AND DH2n AND
NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK)
OR (PORTB(6).PIN AND DH0n AND DH2n AND
NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK)
OR (PORTD(6).PIN AND DH0n AND NOT DH2n AND
XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK));
FDCPE_DD7_BUFR_2_: FDCPE port map (DD(7)_BUFR_2_,DD_D(7)_BUFR_2_,NOT DIORn,'0','0');
DD_D(7)_BUFR_2_ <= (PORTB(7).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n);
FDCPE_DD7_BUFR_1_: FDCPE port map (DD(7)_BUFR_1_,DD_D(7)_BUFR_1_,NOT DIORn,'0','0');
DD_D(7)_BUFR_1_ <= ((PORTE(7).PIN AND DH1n AND NOT DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTD(7).PIN AND DH1n AND NOT DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK));
FDCPE_DD7_BUFR_0_: FDCPE port map (DD(7)_BUFR_0_,DD_D(7)_BUFR_0_,NOT DIORn,'0','0');
DD_D(7)_BUFR_0_ <= ((PORTA(7).PIN AND NOT DH0n AND DH1n AND DH3n AND
XLXI_178/XLXN_449.LFBK)
OR (PORTC(7).PIN AND NOT DH0n AND NOT DH1n AND DH3n AND
XLXI_178/XLXN_449.LFBK));
DD_I(7) <= DD(7)_BUFR;
FTCPE_DH0n: FTCPE port map (DH0n,DH0n_T,DIOWn,'0',NOT RESETn);
DH0n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(0).PIN AND XLXI_178/XLXN_447.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(0).PIN AND NOT XLXI_178/XLXN_447.LFBK));
FTCPE_DH1n: FTCPE port map (DH1n,DH1n_T,DIOWn,'0',NOT RESETn);
DH1n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(1).PIN AND XLXI_178/XLXN_448.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(1).PIN AND NOT XLXI_178/XLXN_448.LFBK));
FTCPE_DH2n: FTCPE port map (DH2n,DH2n_T,DIOWn,'0',NOT RESETn);
DH2n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(2).PIN AND XLXI_178/XLXN_449.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(2).PIN AND NOT XLXI_178/XLXN_449.LFBK));
FTCPE_DH3n: FTCPE port map (DH3n,DH3n_T,DIOWn,'0',NOT RESETn);
DH3n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(3).PIN AND XLXI_178/XLXN_450.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(3).PIN AND NOT XLXI_178/XLXN_450.LFBK));
FTCPE_PORTA0: FTCPE port map (PORTA_I(0),PORTA_T(0),DIOWn,NOT RESETn,'0');
PORTA_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_85/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_85/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_85/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_85/DAT(0).LFBK));
PORTA(0) <= PORTA_I(0) when PORTA_OE(0) = '1' else 'Z';
PORTA_OE(0) <= XLXI_85/DIR(0).LFBK;
FTCPE_PORTA1: FTCPE port map (PORTA_I(1),PORTA_T(1),DIOWn,NOT RESETn,'0');
PORTA_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(1).LFBK));
PORTA(1) <= PORTA_I(1) when PORTA_OE(1) = '1' else 'Z';
PORTA_OE(1) <= XLXI_85/DIR(1).LFBK;
FTCPE_PORTA2: FTCPE port map (PORTA_I(2),PORTA_T(2),DIOWn,NOT RESETn,'0');
PORTA_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DAT(2).LFBK));
PORTA(2) <= PORTA_I(2) when PORTA_OE(2) = '1' else 'Z';
PORTA_OE(2) <= XLXI_85/DIR(2).LFBK;
FTCPE_PORTA3: FTCPE port map (PORTA_I(3),PORTA_T(3),DIOWn,NOT RESETn,'0');
PORTA_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(3).LFBK));
PORTA(3) <= PORTA_I(3) when PORTA_OE(3) = '1' else 'Z';
PORTA_OE(3) <= XLXI_85/DIR(3).LFBK;
FTCPE_PORTA4: FTCPE port map (PORTA_I(4),PORTA_T(4),DIOWn,NOT RESETn,'0');
PORTA_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_85/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_85/DAT(4).LFBK));
PORTA(4) <= PORTA_I(4) when PORTA_OE(4) = '1' else 'Z';
PORTA_OE(4) <= XLXI_85/DIR(4).LFBK;
FTCPE_PORTA5: FTCPE port map (PORTA_I(5),PORTA_T(5),DIOWn,NOT RESETn,'0');
PORTA_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(5).LFBK));
PORTA(5) <= PORTA_I(5) when PORTA_OE(5) = '1' else 'Z';
PORTA_OE(5) <= XLXI_85/DIR(5).LFBK;
FTCPE_PORTA6: FTCPE port map (PORTA_I(6),PORTA_T(6),DIOWn,NOT RESETn,'0');
PORTA_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DAT(6).LFBK));
PORTA(6) <= PORTA_I(6) when PORTA_OE(6) = '1' else 'Z';
PORTA_OE(6) <= XLXI_85/DIR(6).LFBK;
FTCPE_PORTA7: FTCPE port map (PORTA_I(7),PORTA_T(7),DIOWn,NOT RESETn,'0');
PORTA_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DAT(7).LFBK));
PORTA(7) <= PORTA_I(7) when PORTA_OE(7) = '1' else 'Z';
PORTA_OE(7) <= XLXI_85/DIR(7).LFBK;
FTCPE_PORTB0: FTCPE port map (PORTB_I(0),PORTB_T(0),DIOWn,NOT RESETn,'0');
PORTB_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DAT(0).LFBK));
PORTB(0) <= PORTB_I(0) when PORTB_OE(0) = '1' else 'Z';
PORTB_OE(0) <= XLXI_82/DIR(0).LFBK;
FTCPE_PORTB1: FTCPE port map (PORTB_I(1),PORTB_T(1),DIOWn,NOT RESETn,'0');
PORTB_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DAT(1).LFBK));
PORTB(1) <= PORTB_I(1) when PORTB_OE(1) = '1' else 'Z';
PORTB_OE(1) <= XLXI_82/DIR(1).LFBK;
FTCPE_PORTB2: FTCPE port map (PORTB_I(2),PORTB_T(2),DIOWn,NOT RESETn,'0');
PORTB_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DAT(2).LFBK));
PORTB(2) <= PORTB_I(2) when PORTB_OE(2) = '1' else 'Z';
PORTB_OE(2) <= XLXI_82/DIR(2).LFBK;
FTCPE_PORTB3: FTCPE port map (PORTB_I(3),PORTB_T(3),DIOWn,NOT RESETn,'0');
PORTB_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DAT(3).LFBK));
PORTB(3) <= PORTB_I(3) when PORTB_OE(3) = '1' else 'Z';
PORTB_OE(3) <= XLXI_82/DIR(3).LFBK;
FTCPE_PORTB4: FTCPE port map (PORTB_I(4),PORTB_T(4),DIOWn,NOT RESETn,'0');
PORTB_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(4).LFBK));
PORTB(4) <= PORTB_I(4) when PORTB_OE(4) = '1' else 'Z';
PORTB_OE(4) <= XLXI_82/DIR(4).LFBK;
FTCPE_PORTB5: FTCPE port map (PORTB_I(5),PORTB_T(5),DIOWn,NOT RESETn,'0');
PORTB_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(5).LFBK));
PORTB(5) <= PORTB_I(5) when PORTB_OE(5) = '1' else 'Z';
PORTB_OE(5) <= XLXI_82/DIR(5).LFBK;
FTCPE_PORTB6: FTCPE port map (PORTB_I(6),PORTB_T(6),DIOWn,NOT RESETn,'0');
PORTB_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DAT(6).LFBK));
PORTB(6) <= PORTB_I(6) when PORTB_OE(6) = '1' else 'Z';
PORTB_OE(6) <= XLXI_82/DIR(6).LFBK;
FTCPE_PORTB7: FTCPE port map (PORTB_I(7),PORTB_T(7),DIOWn,NOT RESETn,'0');
PORTB_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DAT(7).LFBK));
PORTB(7) <= PORTB_I(7) when PORTB_OE(7) = '1' else 'Z';
PORTB_OE(7) <= XLXI_82/DIR(7).LFBK;
FTCPE_PORTC0: FTCPE port map (PORTC_I(0),PORTC_T(0),DIOWn,NOT RESETn,'0');
PORTC_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_87/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_87/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_87/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_87/DAT(0).LFBK));
PORTC(0) <= PORTC_I(0) when PORTC_OE(0) = '1' else 'Z';
PORTC_OE(0) <= XLXI_87/DIR(0).LFBK;
FTCPE_PORTC1: FTCPE port map (PORTC_I(1),PORTC_T(1),DIOWn,NOT RESETn,'0');
PORTC_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(1).LFBK));
PORTC(1) <= PORTC_I(1) when PORTC_OE(1) = '1' else 'Z';
PORTC_OE(1) <= XLXI_87/DIR(1).LFBK;
FTCPE_PORTC2: FTCPE port map (PORTC_I(2),PORTC_T(2),DIOWn,NOT RESETn,'0');
PORTC_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DAT(2).LFBK));
PORTC(2) <= PORTC_I(2) when PORTC_OE(2) = '1' else 'Z';
PORTC_OE(2) <= XLXI_87/DIR(2).LFBK;
FTCPE_PORTC3: FTCPE port map (PORTC_I(3),PORTC_T(3),DIOWn,NOT RESETn,'0');
PORTC_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(3).LFBK));
PORTC(3) <= PORTC_I(3) when PORTC_OE(3) = '1' else 'Z';
PORTC_OE(3) <= XLXI_87/DIR(3).LFBK;
FTCPE_PORTC4: FTCPE port map (PORTC_I(4),PORTC_T(4),DIOWn,NOT RESETn,'0');
PORTC_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_87/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_87/DAT(4).LFBK));
PORTC(4) <= PORTC_I(4) when PORTC_OE(4) = '1' else 'Z';
PORTC_OE(4) <= XLXI_87/DIR(4).LFBK;
FTCPE_PORTC5: FTCPE port map (PORTC_I(5),PORTC_T(5),DIOWn,NOT RESETn,'0');
PORTC_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(5).LFBK));
PORTC(5) <= PORTC_I(5) when PORTC_OE(5) = '1' else 'Z';
PORTC_OE(5) <= XLXI_87/DIR(5).LFBK;
FTCPE_PORTC6: FTCPE port map (PORTC_I(6),PORTC_T(6),DIOWn,NOT RESETn,'0');
PORTC_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(6).LFBK));
PORTC(6) <= PORTC_I(6) when PORTC_OE(6) = '1' else 'Z';
PORTC_OE(6) <= XLXI_87/DIR(6).LFBK;
FTCPE_PORTC7: FTCPE port map (PORTC_I(7),PORTC_T(7),DIOWn,NOT RESETn,'0');
PORTC_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(7).LFBK));
PORTC(7) <= PORTC_I(7) when PORTC_OE(7) = '1' else 'Z';
PORTC_OE(7) <= XLXI_87/DIR(7).LFBK;
FTCPE_PORTD0: FTCPE port map (PORTD_I(0),PORTD_T(0),DIOWn,NOT RESETn,'0');
PORTD_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_86/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_86/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_86/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_86/DAT(0).LFBK));
PORTD(0) <= PORTD_I(0) when PORTD_OE(0) = '1' else 'Z';
PORTD_OE(0) <= XLXI_86/DIR(0).LFBK;
FTCPE_PORTD1: FTCPE port map (PORTD_I(1),PORTD_T(1),DIOWn,NOT RESETn,'0');
PORTD_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(1).LFBK));
PORTD(1) <= PORTD_I(1) when PORTD_OE(1) = '1' else 'Z';
PORTD_OE(1) <= XLXI_86/DIR(1).LFBK;
FTCPE_PORTD2: FTCPE port map (PORTD_I(2),PORTD_T(2),DIOWn,NOT RESETn,'0');
PORTD_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DAT(2).LFBK));
PORTD(2) <= PORTD_I(2) when PORTD_OE(2) = '1' else 'Z';
PORTD_OE(2) <= XLXI_86/DIR(2).LFBK;
FTCPE_PORTD3: FTCPE port map (PORTD_I(3),PORTD_T(3),DIOWn,NOT RESETn,'0');
PORTD_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(3).LFBK));
PORTD(3) <= PORTD_I(3) when PORTD_OE(3) = '1' else 'Z';
PORTD_OE(3) <= XLXI_86/DIR(3).LFBK;
FTCPE_PORTD4: FTCPE port map (PORTD_I(4),PORTD_T(4),DIOWn,NOT RESETn,'0');
PORTD_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_86/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_86/DAT(4).LFBK));
PORTD(4) <= PORTD_I(4) when PORTD_OE(4) = '1' else 'Z';
PORTD_OE(4) <= XLXI_86/DIR(4).LFBK;
FTCPE_PORTD5: FTCPE port map (PORTD_I(5),PORTD_T(5),DIOWn,NOT RESETn,'0');
PORTD_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(5).LFBK));
PORTD(5) <= PORTD_I(5) when PORTD_OE(5) = '1' else 'Z';
PORTD_OE(5) <= XLXI_86/DIR(5).LFBK;
FTCPE_PORTD6: FTCPE port map (PORTD_I(6),PORTD_T(6),DIOWn,NOT RESETn,'0');
PORTD_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(6).LFBK));
PORTD(6) <= PORTD_I(6) when PORTD_OE(6) = '1' else 'Z';
PORTD_OE(6) <= XLXI_86/DIR(6).LFBK;
FTCPE_PORTD7: FTCPE port map (PORTD_I(7),PORTD_T(7),DIOWn,NOT RESETn,'0');
PORTD_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(7).LFBK));
PORTD(7) <= PORTD_I(7) when PORTD_OE(7) = '1' else 'Z';
PORTD_OE(7) <= XLXI_86/DIR(7).LFBK;
FTCPE_PORTE0: FTCPE port map (PORTE_I(0),PORTE_T(0),DIOWn,NOT RESETn,'0');
PORTE_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DAT(0).LFBK));
PORTE(0) <= PORTE_I(0) when PORTE_OE(0) = '1' else 'Z';
PORTE_OE(0) <= XLXI_80/DIR(0).LFBK;
FTCPE_PORTE1: FTCPE port map (PORTE_I(1),PORTE_T(1),DIOWn,NOT RESETn,'0');
PORTE_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DAT(1).LFBK));
PORTE(1) <= PORTE_I(1) when PORTE_OE(1) = '1' else 'Z';
PORTE_OE(1) <= XLXI_80/DIR(1).LFBK;
FTCPE_PORTE2: FTCPE port map (PORTE_I(2),PORTE_T(2),DIOWn,NOT RESETn,'0');
PORTE_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DAT(2).LFBK));
PORTE(2) <= PORTE_I(2) when PORTE_OE(2) = '1' else 'Z';
PORTE_OE(2) <= XLXI_80/DIR(2).LFBK;
FTCPE_PORTE3: FTCPE port map (PORTE_I(3),PORTE_T(3),DIOWn,NOT RESETn,'0');
PORTE_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DAT(3).LFBK));
PORTE(3) <= PORTE_I(3) when PORTE_OE(3) = '1' else 'Z';
PORTE_OE(3) <= XLXI_80/DIR(3).LFBK;
FTCPE_PORTE4: FTCPE port map (PORTE_I(4),PORTE_T(4),DIOWn,NOT RESETn,'0');
PORTE_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
NOT XLXI_80/DAT(4).LFBK AND XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_80/DAT(4).LFBK AND NOT XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_80/DAT(4).LFBK AND XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
XLXI_80/DAT(4).LFBK AND NOT XLXI_178/XLXN_43.LFBK));
PORTE(4) <= PORTE_I(4) when PORTE_OE(4) = '1' else 'Z';
PORTE_OE(4) <= XLXI_80/DIR(4).LFBK;
FTCPE_PORTE5: FTCPE port map (PORTE_I(5),PORTE_T(5),DIOWn,NOT RESETn,'0');
PORTE_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_80/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_80/DAT(5).LFBK));
PORTE(5) <= PORTE_I(5) when PORTE_OE(5) = '1' else 'Z';
PORTE_OE(5) <= XLXI_80/DIR(5).LFBK;
FTCPE_PORTE6: FTCPE port map (PORTE_I(6),PORTE_T(6),DIOWn,NOT RESETn,'0');
PORTE_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DAT(6).LFBK));
PORTE(6) <= PORTE_I(6) when PORTE_OE(6) = '1' else 'Z';
PORTE_OE(6) <= XLXI_80/DIR(6).LFBK;
FTCPE_PORTE7: FTCPE port map (PORTE_I(7),PORTE_T(7),DIOWn,NOT RESETn,'0');
PORTE_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DAT(7).LFBK));
PORTE(7) <= PORTE_I(7) when PORTE_OE(7) = '1' else 'Z';
PORTE_OE(7) <= XLXI_80/DIR(7).LFBK;
REO <= NOT (((NOT DMACKn)
OR (NOT CS1n)
OR (DMARQ)
OR (CS0n)
OR (NOT DH3n)
OR (EXP0_.EXP)));
SELECTEDn <= XLXI_178/XLXN_43
XOR
SELECTEDn <= CSEL;
FTCPE_XLXI_178/XLXN_43: FTCPE port map (XLXI_178/XLXN_43,XLXI_178/XLXN_43_T,DIOWn,NOT RESETn,'0');
XLXI_178/XLXN_43_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND XLXI_178/XLXN_43.LFBK));
FTCPE_XLXI_80/DIR0: FTCPE port map (XLXI_80/DIR(0),XLXI_80/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DIR(0).LFBK));
FTCPE_XLXI_80/DIR1: FTCPE port map (XLXI_80/DIR(1),XLXI_80/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DIR(1).LFBK));
FTCPE_XLXI_80/DIR2: FTCPE port map (XLXI_80/DIR(2),XLXI_80/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DIR(2).LFBK));
FTCPE_XLXI_80/DIR3: FTCPE port map (XLXI_80/DIR(3),XLXI_80/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_80/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_80/DIR(3).LFBK));
FTCPE_XLXI_80/DIR4: FTCPE port map (XLXI_80/DIR(4),XLXI_80/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(4).LFBK));
FTCPE_XLXI_80/DIR5: FTCPE port map (XLXI_80/DIR(5),XLXI_80/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(5).LFBK));
FTCPE_XLXI_80/DIR6: FTCPE port map (XLXI_80/DIR(6),XLXI_80/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(6).LFBK));
FTCPE_XLXI_80/DIR7: FTCPE port map (XLXI_80/DIR(7),XLXI_80/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(7).LFBK));
FTCPE_XLXI_82/DIR0: FTCPE port map (XLXI_82/DIR(0),XLXI_82/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DIR(0).LFBK));
FTCPE_XLXI_82/DIR1: FTCPE port map (XLXI_82/DIR(1),XLXI_82/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DIR(1).LFBK));
FTCPE_XLXI_82/DIR2: FTCPE port map (XLXI_82/DIR(2),XLXI_82/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DIR(2).LFBK));
FTCPE_XLXI_82/DIR3: FTCPE port map (XLXI_82/DIR(3),XLXI_82/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DIR(3).LFBK));
FTCPE_XLXI_82/DIR4: FTCPE port map (XLXI_82/DIR(4),XLXI_82/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(4).LFBK));
FTCPE_XLXI_82/DIR5: FTCPE port map (XLXI_82/DIR(5),XLXI_82/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(5).LFBK));
FTCPE_XLXI_82/DIR6: FTCPE port map (XLXI_82/DIR(6),XLXI_82/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DIR(6).LFBK));
FTCPE_XLXI_82/DIR7: FTCPE port map (XLXI_82/DIR(7),XLXI_82/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DIR(7).LFBK));
FTCPE_XLXI_85/DIR0: FTCPE port map (XLXI_85/DIR(0),XLXI_85/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_85/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_85/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_85/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_85/DIR(0).LFBK));
FTCPE_XLXI_85/DIR1: FTCPE port map (XLXI_85/DIR(1),XLXI_85/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(1).LFBK));
FTCPE_XLXI_85/DIR2: FTCPE port map (XLXI_85/DIR(2),XLXI_85/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DIR(2).LFBK));
FTCPE_XLXI_85/DIR3: FTCPE port map (XLXI_85/DIR(3),XLXI_85/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(3).LFBK));
FTCPE_XLXI_85/DIR4: FTCPE port map (XLXI_85/DIR(4),XLXI_85/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_85/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_85/DIR(4).LFBK));
FTCPE_XLXI_85/DIR5: FTCPE port map (XLXI_85/DIR(5),XLXI_85/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(5).LFBK));
FTCPE_XLXI_85/DIR6: FTCPE port map (XLXI_85/DIR(6),XLXI_85/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DIR(6).LFBK));
FTCPE_XLXI_85/DIR7: FTCPE port map (XLXI_85/DIR(7),XLXI_85/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DIR(7).LFBK));
FTCPE_XLXI_86/DIR0: FTCPE port map (XLXI_86/DIR(0),XLXI_86/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_86/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_86/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_86/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_86/DIR(0).LFBK));
FTCPE_XLXI_86/DIR1: FTCPE port map (XLXI_86/DIR(1),XLXI_86/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(1).LFBK));
FTCPE_XLXI_86/DIR2: FTCPE port map (XLXI_86/DIR(2),XLXI_86/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DIR(2).LFBK));
FTCPE_XLXI_86/DIR3: FTCPE port map (XLXI_86/DIR(3),XLXI_86/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(3).LFBK));
FTCPE_XLXI_86/DIR4: FTCPE port map (XLXI_86/DIR(4),XLXI_86/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_86/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_86/DIR(4).LFBK));
FTCPE_XLXI_86/DIR5: FTCPE port map (XLXI_86/DIR(5),XLXI_86/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(5).LFBK));
FTCPE_XLXI_86/DIR6: FTCPE port map (XLXI_86/DIR(6),XLXI_86/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(6).LFBK));
FTCPE_XLXI_86/DIR7: FTCPE port map (XLXI_86/DIR(7),XLXI_86/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(7).LFBK));
FTCPE_XLXI_87/DIR0: FTCPE port map (XLXI_87/DIR(0),XLXI_87/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_87/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_87/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_87/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_87/DIR(0).LFBK));
FTCPE_XLXI_87/DIR1: FTCPE port map (XLXI_87/DIR(1),XLXI_87/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(1).LFBK));
FTCPE_XLXI_87/DIR2: FTCPE port map (XLXI_87/DIR(2),XLXI_87/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DIR(2).LFBK));
FTCPE_XLXI_87/DIR3: FTCPE port map (XLXI_87/DIR(3),XLXI_87/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(3).LFBK));
FTCPE_XLXI_87/DIR4: FTCPE port map (XLXI_87/DIR(4),XLXI_87/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_87/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_87/DIR(4).LFBK));
FTCPE_XLXI_87/DIR5: FTCPE port map (XLXI_87/DIR(5),XLXI_87/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(5).LFBK));
FTCPE_XLXI_87/DIR6: FTCPE port map (XLXI_87/DIR(6),XLXI_87/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(6).LFBK));
FTCPE_XLXI_87/DIR7: FTCPE port map (XLXI_87/DIR(7),XLXI_87/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(7).LFBK));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95108-10-PC84
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
| 12 74 |
| 13 73 |
| 14 72 |
| 15 71 |
| 16 70 |
| 17 69 |
| 18 68 |
| 19 67 |
| 20 66 |
| 21 XC95108-10-PC84 65 |
| 22 64 |
| 23 63 |
| 24 62 |
| 25 61 |
| 26 60 |
| 27 59 |
| 28 58 |
| 29 57 |
| 30 56 |
| 31 55 |
| 32 54 |
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 DD<4> 43 DH3n
2 PORTE<0> 44 DA0
3 PORTE<1> 45 DD<0>
4 PORTB<0> 46 DD<5>
5 PORTB<1> 47 PORTA<7>
6 PORTA<0> 48 PORTD<5>
7 PORTD<0> 49 GND
8 GND 50 PORTD<7>
9 DIOWn 51 PORTC<5>
10 DIORn 52 PORTC<7>
11 PORTC<0> 53 SELECTEDn
12 PGND 54 CS0n
13 DH0n 55 DMARQ
14 DD<1> 56 DMACKn
15 PORTE<4> 57 REO
16 GND 58 DD<2>
17 PORTE<5> 59 TDO
18 PORTB<4> 60 GND
19 PORTB<5> 61 PORTE<6>
20 PORTA<4> 62 PORTE<7>
21 PORTD<4> 63 PORTB<6>
22 VCC 64 VCC
23 PORTC<4> 65 PORTB<7>
24 DD<7> 66 PORTA<6>
25 PGND 67 PORTD<6>
26 DA2 68 PORTC<6>
27 GND 69 CS1n
28 TDI 70 DA1
29 TMS 71 DD<3>
30 TCK 72 PORTE<2>
31 CSEL 73 VCC
32 DD<6> 74 RESETn
33 PORTA<1> 75 PORTE<3>
34 PORTA<3> 76 REI
35 PORTA<5> 77 PGND
36 PORTD<1> 78 VCC
37 PORTD<3> 79 PORTB<2>
38 VCC 80 PORTB<3>
39 PORTC<1> 81 PORTA<2>
40 PORTC<3> 82 PORTD<2>
41 DH1n 83 PORTC<2>
42 GND 84 DH2n
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95108-10-PC84
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : STD
Ground on Unused IOs : ON
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25