cpldfit: version I.27 Xilinx Inc.
Fitter Report
Design Name: ata_port_05a1 Date: 11-18-2006, 5:56PM
Device Used: XC95144-10-PQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
95 /144 ( 66%) 423 /720 ( 59%) 240/288 ( 83%) 93 /144 ( 65%) 58 /81 ( 72%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 15/18 30/36 30 67/90 7/11
FB2 10/18 26/36 26 43/90 6/10
FB3 16/18 30/36 30 69/90 7/10
FB4 15/18 30/36 30 67/90 7/10
FB5 15/18 29/36 29 62/90 8/10
FB6 12/18 30/36 30 61/90 7/10
FB7 6/18 31/36 31 27/90 6/10
FB8 6/18 34/36 34 27/90 6/10
----- ----- ----- -----
95/144 240/288 423/720 54/81
* - Resource is exhausted
** Global Control Resources **
Signal 'DIOWn' mapped onto global clock net GCK1.
The complement of 'DIORn' mapped onto global clock net GCK2.
Signal 'REI' mapped onto global output enable net GTS3.
The complement of 'RESETn' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 8 8 | I/O : 60 73
Output : 6 6 | GCK/IO : 2 3
Bidirectional : 48 48 | GTS/IO : 3 4
GCK : 2 2 | GSR/IO : 1 1
GTS : 1 1 |
GSR : 1 1 |
---- ----
Total 66 66
** Power Data **
There are 95 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 54 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
PORTE<0> 5 16 FB1_2 13 I/O I/O STD SLOW RESET
PORTE<1> 5 16 FB1_3 14 I/O I/O STD SLOW RESET
PORTB<0> 5 16 FB1_5 15 I/O I/O STD SLOW RESET
PORTB<1> 5 16 FB1_6 16 I/O I/O STD SLOW RESET
PORTA<0> 5 16 FB1_8 17 I/O I/O STD SLOW RESET
PORTD<0> 5 16 FB1_9 18 I/O I/O STD SLOW RESET
PORTC<0> 5 16 FB1_11 19 I/O I/O STD SLOW RESET
PORTB<3> 5 16 FB2_6 4 GTS/I/O I/O STD SLOW RESET
PORTA<2> 5 16 FB2_8 5 GTS/I/O I/O STD SLOW RESET
PORTD<2> 5 16 FB2_11 8 I/O I/O STD SLOW RESET
PORTC<2> 5 16 FB2_12 9 I/O I/O STD SLOW RESET
DH2n 2 9 FB2_14 10 I/O O STD SLOW SET
PORTE<3> 5 16 FB2_15 11 I/O I/O STD SLOW RESET
PORTE<4> 5 16 FB3_5 26 I/O I/O STD SLOW RESET
PORTE<5> 5 16 FB3_6 27 I/O I/O STD SLOW RESET
PORTB<4> 5 16 FB3_9 30 I/O I/O STD SLOW RESET
PORTB<5> 5 16 FB3_11 31 I/O I/O STD SLOW RESET
PORTA<4> 5 16 FB3_12 32 I/O I/O STD SLOW RESET
PORTD<4> 5 16 FB3_14 34 I/O I/O STD SLOW RESET
PORTC<4> 5 16 FB3_15 35 I/O I/O STD SLOW RESET
PORTE<6> 5 16 FB4_2 89 I/O I/O STD SLOW RESET
PORTE<7> 5 16 FB4_5 91 I/O I/O STD SLOW RESET
PORTB<6> 5 16 FB4_6 92 I/O I/O STD SLOW RESET
PORTB<7> 5 16 FB4_9 94 I/O I/O STD SLOW RESET
PORTA<6> 5 16 FB4_11 95 I/O I/O STD SLOW RESET
PORTD<6> 5 16 FB4_12 96 I/O I/O STD SLOW RESET
PORTC<6> 5 16 FB4_15 98 I/O I/O STD SLOW RESET
PORTA<1> 5 16 FB5_2 37 I/O I/O STD SLOW RESET
PORTA<3> 5 16 FB5_5 38 I/O I/O STD SLOW RESET
PORTD<1> 5 16 FB5_6 39 I/O I/O STD SLOW RESET
PORTD<3> 5 16 FB5_8 41 I/O I/O STD SLOW RESET
PORTC<1> 5 16 FB5_9 42 I/O I/O STD SLOW RESET
PORTC<3> 5 16 FB5_11 43 I/O I/O STD SLOW RESET
DH1n 2 9 FB5_12 44 I/O O STD SLOW SET
DH3n 2 9 FB5_14 45 I/O O STD SLOW SET
REO 11 14 FB6_2 76 I/O O STD SLOW
PORTA<5> 5 16 FB6_5 78 I/O I/O STD SLOW RESET
PORTA<7> 5 16 FB6_6 79 I/O I/O STD SLOW RESET
PORTD<5> 5 16 FB6_9 81 I/O I/O STD SLOW RESET
PORTD<7> 5 16 FB6_11 82 I/O I/O STD SLOW RESET
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
PORTC<5> 5 16 FB6_12 83 I/O I/O STD SLOW RESET
PORTC<7> 5 16 FB6_15 87 I/O I/O STD SLOW RESET
DD<0> 5 9 FB7_2 52 I/O I/O STD SLOW RESET
DD<1> 5 9 FB7_6 55 I/O I/O STD SLOW RESET
DD<2> 5 9 FB7_9 57 I/O I/O STD SLOW RESET
DD<3> 5 9 FB7_12 60 I/O I/O STD SLOW RESET
DD<4> 5 9 FB7_15 62 I/O I/O STD SLOW RESET
SELECTEDn 2 2 FB7_17 63 I/O O STD SLOW
DD<5> 5 9 FB8_2 65 I/O I/O STD SLOW RESET
DD<6> 5 9 FB8_6 67 I/O I/O STD SLOW RESET
DD<7> 5 9 FB8_9 69 I/O I/O STD SLOW RESET
PORTE<2> 5 16 FB8_12 72 I/O I/O STD SLOW RESET
PORTB<2> 5 16 FB8_15 74 I/O I/O STD SLOW RESET
DH0n 2 9 FB8_17 75 I/O O STD SLOW SET
** 41 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_87/DIR<0> 4 15 FB1_10 STD RESET
XLXI_86/DIR<0> 4 15 FB1_12 STD RESET
XLXI_85/DIR<1> 4 15 FB1_13 STD RESET
XLXI_85/DIR<0> 4 15 FB1_14 STD RESET
XLXI_82/DIR<1> 4 15 FB1_15 STD RESET
XLXI_82/DIR<0> 4 15 FB1_16 STD RESET
XLXI_80/DIR<1> 4 15 FB1_17 STD RESET
XLXI_80/DIR<0> 4 15 FB1_18 STD RESET
XLXI_87/DIR<2> 4 15 FB2_13 STD RESET
XLXI_86/DIR<2> 4 15 FB2_16 STD RESET
XLXI_85/DIR<2> 4 15 FB2_17 STD RESET
XLXI_82/DIR<2> 4 15 FB2_18 STD RESET
XLXI_178/XLXN_43 2 9 FB3_3 STD RESET
XLXI_87/DIR<4> 4 15 FB3_4 STD RESET
XLXI_86/DIR<4> 4 15 FB3_7 STD RESET
XLXI_85/DIR<5> 4 15 FB3_8 STD RESET
XLXI_85/DIR<4> 4 15 FB3_10 STD RESET
XLXI_82/DIR<5> 4 15 FB3_13 STD RESET
XLXI_82/DIR<4> 4 15 FB3_16 STD RESET
XLXI_80/DIR<5> 4 15 FB3_17 STD RESET
XLXI_80/DIR<4> 4 15 FB3_18 STD RESET
XLXI_87/DIR<6> 4 15 FB4_7 STD RESET
XLXI_86/DIR<6> 4 15 FB4_8 STD RESET
XLXI_85/DIR<7> 4 15 FB4_10 STD RESET
XLXI_85/DIR<6> 4 15 FB4_13 STD RESET
XLXI_82/DIR<7> 4 15 FB4_14 STD RESET
XLXI_82/DIR<6> 4 15 FB4_16 STD RESET
XLXI_80/DIR<7> 4 15 FB4_17 STD RESET
XLXI_80/DIR<6> 4 15 FB4_18 STD RESET
XLXI_87/DIR<3> 4 15 FB5_7 STD RESET
XLXI_87/DIR<1> 4 15 FB5_10 STD RESET
XLXI_86/DIR<3> 4 15 FB5_13 STD RESET
XLXI_86/DIR<1> 4 15 FB5_15 STD RESET
XLXI_85/DIR<3> 4 15 FB5_16 STD RESET
XLXI_82/DIR<3> 4 15 FB5_17 STD RESET
XLXI_80/DIR<3> 4 15 FB5_18 STD RESET
XLXI_87/DIR<7> 4 15 FB6_13 STD RESET
XLXI_87/DIR<5> 4 15 FB6_14 STD RESET
XLXI_86/DIR<7> 4 15 FB6_16 STD RESET
XLXI_86/DIR<5> 4 15 FB6_17 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_80/DIR<2> 4 15 FB6_18 STD RESET
** 12 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
DIOWn FB1_17 24~ GCK/I/O GCK
RESETn FB2_2 1~ GSR/I/O GSR
REI FB2_5 3~ GTS/I/O GTS
DIORn FB3_2 25~ GCK/I/O GCK/I
CSEL FB4_8 93 I/O I
DA2 FB4_14 97 I/O I
DA0 FB4_17 99 I/O I
CS0n FB6_8 80 I/O I
DMARQ FB7_5 54 I/O I
DMACKn FB7_11 58 I/O I
DA1 FB8_5 66 I/O I
CS1n FB8_11 70 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 30/6
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
PORTE<0> 5 0 0 0 FB1_2 13 I/O I/O
PORTE<1> 5 0 0 0 FB1_3 14 I/O I/O
(unused) 0 0 0 5 FB1_4 (b)
PORTB<0> 5 0 0 0 FB1_5 15 I/O I/O
PORTB<1> 5 0 0 0 FB1_6 16 I/O I/O
(unused) 0 0 0 5 FB1_7 (b)
PORTA<0> 5 0 0 0 FB1_8 17 I/O I/O
PORTD<0> 5 0 0 0 FB1_9 18 I/O I/O
XLXI_87/DIR<0> 4 0 0 1 FB1_10 (b) (b)
PORTC<0> 5 0 0 0 FB1_11 19 I/O I/O
XLXI_86/DIR<0> 4 0 0 1 FB1_12 20 I/O (b)
XLXI_85/DIR<1> 4 0 0 1 FB1_13 (b) (b)
XLXI_85/DIR<0> 4 0 0 1 FB1_14 21 I/O (b)
XLXI_82/DIR<1> 4 0 0 1 FB1_15 22 I/O (b)
XLXI_82/DIR<0> 4 0 0 1 FB1_16 (b) (b)
XLXI_80/DIR<1> 4 0 0 1 FB1_17 24 GCK/I/O GCK
XLXI_80/DIR<0> 4 0 0 1 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 11: DMARQ 21: XLXI_82/DAT<1>.LFBK
2: DA1 12: CS0n 22: XLXI_82/DIR<0>.LFBK
3: DA2 13: XLXI_178/XLXN_43 23: XLXI_82/DIR<1>.LFBK
4: DH0n 14: DMACKn 24: XLXI_85/DAT<0>.LFBK
5: DH1n 15: CS1n 25: XLXI_85/DIR<0>.LFBK
6: DH2n 16: XLXI_80/DAT<0>.LFBK 26: XLXI_85/DIR<1>.LFBK
7: DH3n 17: XLXI_80/DAT<1>.LFBK 27: XLXI_86/DAT<0>.LFBK
8: DD<0>.PIN 18: XLXI_80/DIR<0>.LFBK 28: XLXI_86/DIR<0>.LFBK
9: DD<1>.PIN 19: XLXI_80/DIR<1>.LFBK 29: XLXI_87/DAT<0>.LFBK
10: CSEL 20: XLXI_82/DAT<0>.LFBK 30: XLXI_87/DIR<0>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
PORTE<0> XXXXXXXX.XXXXXXX.X...................... 16 16
PORTE<1> XXXXXXX.XXXXXXX.X.X..................... 16 16
PORTB<0> XXXXXXXX.XXXXXX....X.X.................. 16 16
PORTB<1> XXXXXXX.XXXXXXX.....X.X................. 16 16
PORTA<0> XXXXXXXX.XXXXXX........XX............... 16 16
PORTD<0> XXXXXXXX.XXXXXX...........XX............ 16 16
XLXI_87/DIR<0> XXXXXXXX.XXXXXX..............X.......... 15 15
PORTC<0> XXXXXXXX.XXXXXX.............XX.......... 16 16
XLXI_86/DIR<0> XXXXXXXX.XXXXXX............X............ 15 15
XLXI_85/DIR<1> XXXXXXX.XXXXXXX..........X.............. 15 15
XLXI_85/DIR<0> XXXXXXXX.XXXXXX.........X............... 15 15
XLXI_82/DIR<1> XXXXXXX.XXXXXXX.......X................. 15 15
XLXI_82/DIR<0> XXXXXXXX.XXXXXX......X.................. 15 15
XLXI_80/DIR<1> XXXXXXX.XXXXXXX...X..................... 15 15
XLXI_80/DIR<0> XXXXXXXX.XXXXXX..X...................... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 26/10
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 1 GSR/I/O GSR
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 3 GTS/I/O GTS
PORTB<3> 5 0 0 0 FB2_6 4 GTS/I/O I/O
(unused) 0 0 0 5 FB2_7 (b)
PORTA<2> 5 0 0 0 FB2_8 5 GTS/I/O I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
PORTD<2> 5 0 0 0 FB2_11 8 I/O I/O
PORTC<2> 5 0 0 0 FB2_12 9 I/O I/O
XLXI_87/DIR<2> 4 0 0 1 FB2_13 (b) (b)
DH2n 2 0 0 3 FB2_14 10 I/O O
PORTE<3> 5 0 0 0 FB2_15 11 I/O I/O
XLXI_86/DIR<2> 4 0 0 1 FB2_16 (b) (b)
XLXI_85/DIR<2> 4 0 0 1 FB2_17 12 I/O (b)
XLXI_82/DIR<2> 4 0 0 1 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 10: DMARQ 19: XLXI_82/DIR<2>.LFBK
2: DA1 11: CS0n 20: XLXI_82/DIR<3>
3: DA2 12: XLXI_178/XLXN_43 21: XLXI_85/DAT<2>.LFBK
4: DH0n 13: XLXI_178/XLXN_449.LFBK 22: XLXI_85/DIR<2>.LFBK
5: DH1n 14: DMACKn 23: XLXI_86/DAT<2>.LFBK
6: DH3n 15: CS1n 24: XLXI_86/DIR<2>.LFBK
7: DD<2>.PIN 16: XLXI_80/DAT<3>.LFBK 25: XLXI_87/DAT<2>.LFBK
8: DD<3>.PIN 17: XLXI_80/DIR<3> 26: XLXI_87/DIR<2>.LFBK
9: CSEL 18: XLXI_82/DAT<3>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
PORTB<3> XXXXXX.XXXXXXXX..X.X.................... 16 16
PORTA<2> XXXXXXX.XXXXXXX.....XX.................. 16 16
PORTD<2> XXXXXXX.XXXXXXX.......XX................ 16 16
PORTC<2> XXXXXXX.XXXXXXX.........XX.............. 16 16
XLXI_87/DIR<2> XXXXXXX.XXXXXXX..........X.............. 15 15
DH2n XXX...X..XX.XXX......................... 9 9
PORTE<3> XXXXXX.XXXXXXXXXX....................... 16 16
XLXI_86/DIR<2> XXXXXXX.XXXXXXX........X................ 15 15
XLXI_85/DIR<2> XXXXXXX.XXXXXXX......X.................. 15 15
XLXI_82/DIR<2> XXXXXXX.XXXXXXX...X..................... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 30/6
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 25 GCK/I/O GCK/I
XLXI_178/XLXN_43 2 0 0 3 FB3_3 (b) (b)
XLXI_87/DIR<4> 4 0 0 1 FB3_4 (b) (b)
PORTE<4> 5 0 0 0 FB3_5 26 I/O I/O
PORTE<5> 5 0 0 0 FB3_6 27 I/O I/O
XLXI_86/DIR<4> 4 0 0 1 FB3_7 (b) (b)
XLXI_85/DIR<5> 4 0 0 1 FB3_8 29 GCK/I/O (b)
PORTB<4> 5 0 0 0 FB3_9 30 I/O I/O
XLXI_85/DIR<4> 4 0 0 1 FB3_10 (b) (b)
PORTB<5> 5 0 0 0 FB3_11 31 I/O I/O
PORTA<4> 5 0 0 0 FB3_12 32 I/O I/O
XLXI_82/DIR<5> 4 0 0 1 FB3_13 (b) (b)
PORTD<4> 5 0 0 0 FB3_14 34 I/O I/O
PORTC<4> 5 0 0 0 FB3_15 35 I/O I/O
XLXI_82/DIR<4> 4 0 0 1 FB3_16 (b) (b)
XLXI_80/DIR<5> 4 0 0 1 FB3_17 36 I/O (b)
XLXI_80/DIR<4> 4 0 0 1 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 11: DMARQ 21: XLXI_82/DAT<5>.LFBK
2: DA1 12: CS0n 22: XLXI_82/DIR<4>.LFBK
3: DA2 13: XLXI_178/XLXN_43.LFBK 23: XLXI_82/DIR<5>.LFBK
4: DH0n 14: DMACKn 24: XLXI_85/DAT<4>.LFBK
5: DH1n 15: CS1n 25: XLXI_85/DIR<4>.LFBK
6: DH2n 16: XLXI_80/DAT<4>.LFBK 26: XLXI_85/DIR<5>.LFBK
7: DH3n 17: XLXI_80/DAT<5>.LFBK 27: XLXI_86/DAT<4>.LFBK
8: DD<4>.PIN 18: XLXI_80/DIR<4>.LFBK 28: XLXI_86/DIR<4>.LFBK
9: DD<5>.PIN 19: XLXI_80/DIR<5>.LFBK 29: XLXI_87/DAT<4>.LFBK
10: CSEL 20: XLXI_82/DAT<4>.LFBK 30: XLXI_87/DIR<4>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
XLXI_178/XLXN_43 XXX....X..XXXXX......................... 9 9
XLXI_87/DIR<4> XXXXXXXX.XXXXXX..............X.......... 15 15
PORTE<4> XXXXXXXX.XXXXXXX.X...................... 16 16
PORTE<5> XXXXXXX.XXXXXXX.X.X..................... 16 16
XLXI_86/DIR<4> XXXXXXXX.XXXXXX............X............ 15 15
XLXI_85/DIR<5> XXXXXXX.XXXXXXX..........X.............. 15 15
PORTB<4> XXXXXXXX.XXXXXX....X.X.................. 16 16
XLXI_85/DIR<4> XXXXXXXX.XXXXXX.........X............... 15 15
PORTB<5> XXXXXXX.XXXXXXX.....X.X................. 16 16
PORTA<4> XXXXXXXX.XXXXXX........XX............... 16 16
XLXI_82/DIR<5> XXXXXXX.XXXXXXX.......X................. 15 15
PORTD<4> XXXXXXXX.XXXXXX...........XX............ 16 16
PORTC<4> XXXXXXXX.XXXXXX.............XX.......... 16 16
XLXI_82/DIR<4> XXXXXXXX.XXXXXX......X.................. 15 15
XLXI_80/DIR<5> XXXXXXX.XXXXXXX...X..................... 15 15
XLXI_80/DIR<4> XXXXXXXX.XXXXXX..X...................... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 30/6
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
PORTE<6> 5 0 0 0 FB4_2 89 I/O I/O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
PORTE<7> 5 0 0 0 FB4_5 91 I/O I/O
PORTB<6> 5 0 0 0 FB4_6 92 I/O I/O
XLXI_87/DIR<6> 4 0 0 1 FB4_7 (b) (b)
XLXI_86/DIR<6> 4 0 0 1 FB4_8 93 I/O I
PORTB<7> 5 0 0 0 FB4_9 94 I/O I/O
XLXI_85/DIR<7> 4 0 0 1 FB4_10 (b) (b)
PORTA<6> 5 0 0 0 FB4_11 95 I/O I/O
PORTD<6> 5 0 0 0 FB4_12 96 I/O I/O
XLXI_85/DIR<6> 4 0 0 1 FB4_13 (b) (b)
XLXI_82/DIR<7> 4 0 0 1 FB4_14 97 I/O I
PORTC<6> 5 0 0 0 FB4_15 98 I/O I/O
XLXI_82/DIR<6> 4 0 0 1 FB4_16 (b) (b)
XLXI_80/DIR<7> 4 0 0 1 FB4_17 99 I/O I
XLXI_80/DIR<6> 4 0 0 1 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 11: DMARQ 21: XLXI_82/DAT<7>.LFBK
2: DA1 12: CS0n 22: XLXI_82/DIR<6>.LFBK
3: DA2 13: XLXI_178/XLXN_43 23: XLXI_82/DIR<7>.LFBK
4: DH0n 14: DMACKn 24: XLXI_85/DAT<6>.LFBK
5: DH1n 15: CS1n 25: XLXI_85/DIR<6>.LFBK
6: DH2n 16: XLXI_80/DAT<6>.LFBK 26: XLXI_85/DIR<7>.LFBK
7: DH3n 17: XLXI_80/DAT<7>.LFBK 27: XLXI_86/DAT<6>.LFBK
8: DD<6>.PIN 18: XLXI_80/DIR<6>.LFBK 28: XLXI_86/DIR<6>.LFBK
9: DD<7>.PIN 19: XLXI_80/DIR<7>.LFBK 29: XLXI_87/DAT<6>.LFBK
10: CSEL 20: XLXI_82/DAT<6>.LFBK 30: XLXI_87/DIR<6>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
PORTE<6> XXXXXXXX.XXXXXXX.X...................... 16 16
PORTE<7> XXXXXXX.XXXXXXX.X.X..................... 16 16
PORTB<6> XXXXXXXX.XXXXXX....X.X.................. 16 16
XLXI_87/DIR<6> XXXXXXXX.XXXXXX..............X.......... 15 15
XLXI_86/DIR<6> XXXXXXXX.XXXXXX............X............ 15 15
PORTB<7> XXXXXXX.XXXXXXX.....X.X................. 16 16
XLXI_85/DIR<7> XXXXXXX.XXXXXXX..........X.............. 15 15
PORTA<6> XXXXXXXX.XXXXXX........XX............... 16 16
PORTD<6> XXXXXXXX.XXXXXX...........XX............ 16 16
XLXI_85/DIR<6> XXXXXXXX.XXXXXX.........X............... 15 15
XLXI_82/DIR<7> XXXXXXX.XXXXXXX.......X................. 15 15
PORTC<6> XXXXXXXX.XXXXXX.............XX.......... 16 16
XLXI_82/DIR<6> XXXXXXXX.XXXXXX......X.................. 15 15
XLXI_80/DIR<7> XXXXXXX.XXXXXXX...X..................... 15 15
XLXI_80/DIR<6> XXXXXXXX.XXXXXX..X...................... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 29/7
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
PORTA<1> 5 0 0 0 FB5_2 37 I/O I/O
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 0 5 FB5_4 (b)
PORTA<3> 5 0 0 0 FB5_5 38 I/O I/O
PORTD<1> 5 0 0 0 FB5_6 39 I/O I/O
XLXI_87/DIR<3> 4 0 0 1 FB5_7 (b) (b)
PORTD<3> 5 0 0 0 FB5_8 41 I/O I/O
PORTC<1> 5 0 0 0 FB5_9 42 I/O I/O
XLXI_87/DIR<1> 4 0 0 1 FB5_10 (b) (b)
PORTC<3> 5 0 0 0 FB5_11 43 I/O I/O
DH1n 2 0 0 3 FB5_12 44 I/O O
XLXI_86/DIR<3> 4 0 0 1 FB5_13 (b) (b)
DH3n 2 0 0 3 FB5_14 45 I/O O
XLXI_86/DIR<1> 4 0 0 1 FB5_15 48 I/O (b)
XLXI_85/DIR<3> 4 0 0 1 FB5_16 (b) (b)
XLXI_82/DIR<3> 4 0 0 1 FB5_17 51 I/O (b)
XLXI_80/DIR<3> 4 0 0 1 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 11: XLXI_178/XLXN_43 21: XLXI_85/DIR<3>.LFBK
2: DA1 12: XLXI_178/XLXN_448.LFBK 22: XLXI_86/DAT<1>.LFBK
3: DA2 13: XLXI_178/XLXN_450.LFBK 23: XLXI_86/DAT<3>.LFBK
4: DH0n 14: DMACKn 24: XLXI_86/DIR<1>.LFBK
5: DH2n 15: CS1n 25: XLXI_86/DIR<3>.LFBK
6: DD<1>.PIN 16: XLXI_80/DIR<3>.LFBK 26: XLXI_87/DAT<1>.LFBK
7: DD<3>.PIN 17: XLXI_82/DIR<3>.LFBK 27: XLXI_87/DAT<3>.LFBK
8: CSEL 18: XLXI_85/DAT<1>.LFBK 28: XLXI_87/DIR<1>.LFBK
9: DMARQ 19: XLXI_85/DAT<3>.LFBK 29: XLXI_87/DIR<3>.LFBK
10: CS0n 20: XLXI_85/DIR<1>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
PORTA<1> XXXXXX.XXXXXXXX..X.X.................... 16 16
PORTA<3> XXXXX.XXXXXXXXX...X.X................... 16 16
PORTD<1> XXXXXX.XXXXXXXX......X.X................ 16 16
XLXI_87/DIR<3> XXXXX.XXXXXXXXX.............X........... 15 15
PORTD<3> XXXXX.XXXXXXXXX.......X.X............... 16 16
PORTC<1> XXXXXX.XXXXXXXX..........X.X............ 16 16
XLXI_87/DIR<1> XXXXXX.XXXXXXXX............X............ 15 15
PORTC<3> XXXXX.XXXXXXXXX...........X.X........... 16 16
DH1n XXX..X..XX.X.XX......................... 9 9
XLXI_86/DIR<3> XXXXX.XXXXXXXXX.........X............... 15 15
DH3n XXX...X.XX..XXX......................... 9 9
XLXI_86/DIR<1> XXXXXX.XXXXXXXX........X................ 15 15
XLXI_85/DIR<3> XXXXX.XXXXXXXXX.....X................... 15 15
XLXI_82/DIR<3> XXXXX.XXXXXXXXX.X....................... 15 15
XLXI_80/DIR<3> XXXXX.XXXXXXXXXX........................ 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 30/6
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/3 2 FB6_1 (b) (b)
REO 11 6<- 0 0 FB6_2 76 I/O O
(unused) 0 0 /\3 2 FB6_3 (b) (b)
(unused) 0 0 0 5 FB6_4 (b)
PORTA<5> 5 0 0 0 FB6_5 78 I/O I/O
PORTA<7> 5 0 0 0 FB6_6 79 I/O I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 80 I/O I
PORTD<5> 5 0 0 0 FB6_9 81 I/O I/O
(unused) 0 0 0 5 FB6_10 (b)
PORTD<7> 5 0 0 0 FB6_11 82 I/O I/O
PORTC<5> 5 0 0 0 FB6_12 83 I/O I/O
XLXI_87/DIR<7> 4 0 0 1 FB6_13 (b) (b)
XLXI_87/DIR<5> 4 0 0 1 FB6_14 84 I/O (b)
PORTC<7> 5 0 0 0 FB6_15 87 I/O I/O
XLXI_86/DIR<7> 4 0 0 1 FB6_16 (b) (b)
XLXI_86/DIR<5> 4 0 0 1 FB6_17 88 I/O (b)
XLXI_80/DIR<2> 4 0 0 1 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: DA0 11: DIORn 21: XLXI_85/DIR<5>
2: DA1 12: CSEL 22: XLXI_85/DIR<7>
3: DA2 13: DMARQ 23: XLXI_86/DAT<5>.LFBK
4: DH0n 14: CS0n 24: XLXI_86/DAT<7>.LFBK
5: DH1n 15: XLXI_178/XLXN_43 25: XLXI_86/DIR<5>.LFBK
6: DH2n 16: DMACKn 26: XLXI_86/DIR<7>.LFBK
7: DH3n 17: CS1n 27: XLXI_87/DAT<5>.LFBK
8: DD<2>.PIN 18: XLXI_80/DIR<2>.LFBK 28: XLXI_87/DAT<7>.LFBK
9: DD<5>.PIN 19: XLXI_85/DAT<5>.LFBK 29: XLXI_87/DIR<5>.LFBK
10: DD<7>.PIN 20: XLXI_85/DAT<7>.LFBK 30: XLXI_87/DIR<7>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
REO XXXXXXX...XXXXXXX....................... 14 14
PORTA<5> XXXXXXX.X..XXXXXX.X.X................... 16 16
PORTA<7> XXXXXXX..X.XXXXXX..X.X.................. 16 16
PORTD<5> XXXXXXX.X..XXXXXX.....X.X............... 16 16
PORTD<7> XXXXXXX..X.XXXXXX......X.X.............. 16 16
PORTC<5> XXXXXXX.X..XXXXXX.........X.X........... 16 16
XLXI_87/DIR<7> XXXXXXX..X.XXXXXX............X.......... 15 15
XLXI_87/DIR<5> XXXXXXX.X..XXXXXX...........X........... 15 15
PORTC<7> XXXXXXX..X.XXXXXX..........X.X.......... 16 16
XLXI_86/DIR<7> XXXXXXX..X.XXXXXX........X.............. 15 15
XLXI_86/DIR<5> XXXXXXX.X..XXXXXX.......X............... 15 15
XLXI_80/DIR<2> XXXXXXXX...XXXXXXX...................... 15 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
DD<0> 5 0 0 0 FB7_2 52 I/O I/O
(unused) 0 0 0 5 FB7_3 (b)
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 54 I/O I
DD<1> 5 0 0 0 FB7_6 55 I/O I/O
(unused) 0 0 0 5 FB7_7 (b)
(unused) 0 0 0 5 FB7_8 56 I/O
DD<2> 5 0 0 0 FB7_9 57 I/O I/O
(unused) 0 0 0 5 FB7_10 (b)
(unused) 0 0 0 5 FB7_11 58 I/O I
DD<3> 5 0 0 0 FB7_12 60 I/O I/O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 61 I/O
DD<4> 5 0 0 0 FB7_15 62 I/O I/O
(unused) 0 0 0 5 FB7_16 (b)
SELECTEDn 2 0 0 3 FB7_17 63 I/O O
(unused) 0 0 0 5 FB7_18 (b)
Signals Used by Logic in Function Block
1: DH0n 12: PORTB<2>.PIN 22: PORTD<2>.PIN
2: DH1n 13: PORTB<3>.PIN 23: PORTD<3>.PIN
3: DH2n 14: PORTB<4>.PIN 24: PORTD<4>.PIN
4: DH3n 15: PORTC<0>.PIN 25: PORTE<0>.PIN
5: PORTA<0>.PIN 16: PORTC<1>.PIN 26: PORTE<1>.PIN
6: PORTA<1>.PIN 17: PORTC<2>.PIN 27: PORTE<2>.PIN
7: PORTA<2>.PIN 18: PORTC<3>.PIN 28: PORTE<3>.PIN
8: PORTA<3>.PIN 19: PORTC<4>.PIN 29: PORTE<4>.PIN
9: PORTA<4>.PIN 20: PORTD<0>.PIN 30: CSEL
10: PORTB<0>.PIN 21: PORTD<1>.PIN 31: XLXI_178/XLXN_43
11: PORTB<1>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<0> XXXXX....X....X....X....X............... 9 9
DD<1> XXXX.X....X....X....X....X.............. 9 9
DD<2> XXXX..X....X....X....X....X............. 9 9
DD<3> XXXX...X....X....X....X....X............ 9 9
DD<4> XXXX....X....X....X....X....X........... 9 9
SELECTEDn .............................XX......... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 34/2
Number of signals used by logic mapping into function block: 34
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
DD<5> 5 0 0 0 FB8_2 65 I/O I/O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 66 I/O I
DD<6> 5 0 0 0 FB8_6 67 I/O I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 68 I/O
DD<7> 5 0 0 0 FB8_9 69 I/O I/O
(unused) 0 0 0 5 FB8_10 (b)
(unused) 0 0 0 5 FB8_11 70 I/O I
PORTE<2> 5 0 0 0 FB8_12 72 I/O I/O
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 73 I/O
PORTB<2> 5 0 0 0 FB8_15 74 I/O I/O
(unused) 0 0 0 5 FB8_16 (b)
DH0n 2 0 0 3 FB8_17 75 I/O O
(unused) 0 0 0 5 FB8_18 (b)
Signals Used by Logic in Function Block
1: DA0 13: PORTC<5>.PIN 24: CSEL
2: DA1 14: PORTC<6>.PIN 25: DMARQ
3: DA2 15: PORTC<7>.PIN 26: CS0n
4: DH1n 16: PORTD<5>.PIN 27: XLXI_178/XLXN_43
5: DH2n 17: PORTD<6>.PIN 28: XLXI_178/XLXN_447.LFBK
6: DH3n 18: PORTD<7>.PIN 29: DMACKn
7: PORTA<5>.PIN 19: PORTE<5>.PIN 30: CS1n
8: PORTA<6>.PIN 20: PORTE<6>.PIN 31: XLXI_80/DAT<2>.LFBK
9: PORTA<7>.PIN 21: PORTE<7>.PIN 32: XLXI_80/DIR<2>
10: PORTB<5>.PIN 22: DD<0>.PIN 33: XLXI_82/DAT<2>.LFBK
11: PORTB<6>.PIN 23: DD<2>.PIN 34: XLXI_82/DIR<2>
12: PORTB<7>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DD<5> ...XXXX..X..X..X..X........X............ 9 9
DD<6> ...XXX.X..X..X..X..X.......X............ 9 9
DD<7> ...XXX..X..X..X..X..X......X............ 9 9
PORTE<2> XXXXXX................XXXXXXXXXX........ 16 16
PORTB<2> XXXXXX................XXXXXXXX..XX...... 16 16
DH0n XXX..................X..XX.XXX.......... 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FDCPE_DD0: FDCPE port map (DD_I(0),DD(0),NOT DIORn,'0','0');
DD(0) <= ((PORTA(0).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(0).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(0).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(0).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(0).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD1: FDCPE port map (DD_I(1),DD(1),NOT DIORn,'0','0');
DD(1) <= ((PORTA(1).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(1).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(1).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(1).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(1).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD2: FDCPE port map (DD_I(2),DD(2),NOT DIORn,'0','0');
DD(2) <= ((PORTA(2).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(2).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(2).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(2).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(2).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD3: FDCPE port map (DD_I(3),DD(3),NOT DIORn,'0','0');
DD(3) <= ((PORTA(3).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(3).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(3).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(3).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(3).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD4: FDCPE port map (DD_I(4),DD(4),NOT DIORn,'0','0');
DD(4) <= ((PORTA(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n)
OR (PORTE(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n)
OR (PORTC(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTB(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n)
OR (PORTD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n));
FDCPE_DD5: FDCPE port map (DD_I(5),DD(5),NOT DIORn,'0','0');
DD(5) <= ((PORTA(5).PIN AND DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTE(5).PIN AND DH1n AND NOT DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTC(5).PIN AND NOT DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTB(5).PIN AND NOT DH1n AND DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK)
OR (PORTD(5).PIN AND DH1n AND NOT DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK));
FDCPE_DD6: FDCPE port map (DD_I(6),DD(6),NOT DIORn,'0','0');
DD(6) <= ((PORTA(6).PIN AND DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTE(6).PIN AND DH1n AND NOT DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTC(6).PIN AND NOT DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTB(6).PIN AND NOT DH1n AND DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK)
OR (PORTD(6).PIN AND DH1n AND NOT DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK));
FDCPE_DD7: FDCPE port map (DD_I(7),DD(7),NOT DIORn,'0','0');
DD(7) <= ((PORTA(7).PIN AND DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTE(7).PIN AND DH1n AND NOT DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTC(7).PIN AND NOT DH1n AND DH2n AND DH3n AND
NOT XLXI_178/XLXN_447.LFBK)
OR (PORTB(7).PIN AND NOT DH1n AND DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK)
OR (PORTD(7).PIN AND DH1n AND NOT DH2n AND DH3n AND
XLXI_178/XLXN_447.LFBK));
FTCPE_DH0n: FTCPE port map (DH0n,DH0n_T,DIOWn,'0',NOT RESETn);
DH0n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(0).PIN AND XLXI_178/XLXN_447.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(0).PIN AND NOT XLXI_178/XLXN_447.LFBK));
FTCPE_DH1n: FTCPE port map (DH1n,DH1n_T,DIOWn,'0',NOT RESETn);
DH1n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(1).PIN AND XLXI_178/XLXN_448.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(1).PIN AND NOT XLXI_178/XLXN_448.LFBK));
FTCPE_DH2n: FTCPE port map (DH2n,DH2n_T,DIOWn,'0',NOT RESETn);
DH2n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(2).PIN AND XLXI_178/XLXN_449.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(2).PIN AND NOT XLXI_178/XLXN_449.LFBK));
FTCPE_DH3n: FTCPE port map (DH3n,DH3n_T,DIOWn,'0',NOT RESETn);
DH3n_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(3).PIN AND XLXI_178/XLXN_450.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(3).PIN AND NOT XLXI_178/XLXN_450.LFBK));
FTCPE_PORTA0: FTCPE port map (PORTA_I(0),PORTA_T(0),DIOWn,NOT RESETn,'0');
PORTA_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DAT(0).LFBK));
PORTA(0) <= PORTA_I(0) when PORTA_OE(0) = '1' else 'Z';
PORTA_OE(0) <= XLXI_85/DIR(0).LFBK;
FTCPE_PORTA1: FTCPE port map (PORTA_I(1),PORTA_T(1),DIOWn,NOT RESETn,'0');
PORTA_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_85/DAT(1).LFBK AND XLXI_178/XLXN_448.LFBK AND
XLXI_178/XLXN_450.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_85/DAT(1).LFBK AND XLXI_178/XLXN_448.LFBK AND
XLXI_178/XLXN_450.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_85/DAT(1).LFBK AND XLXI_178/XLXN_448.LFBK AND
XLXI_178/XLXN_450.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_85/DAT(1).LFBK AND XLXI_178/XLXN_448.LFBK AND
XLXI_178/XLXN_450.LFBK));
PORTA(1) <= PORTA_I(1) when PORTA_OE(1) = '1' else 'Z';
PORTA_OE(1) <= XLXI_85/DIR(1);
FTCPE_PORTA2: FTCPE port map (PORTA_I(2),PORTA_T(2),DIOWn,NOT RESETn,'0');
PORTA_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DAT(2).LFBK));
PORTA(2) <= PORTA_I(2) when PORTA_OE(2) = '1' else 'Z';
PORTA_OE(2) <= XLXI_85/DIR(2).LFBK;
FTCPE_PORTA3: FTCPE port map (PORTA_I(3),PORTA_T(3),DIOWn,NOT RESETn,'0');
PORTA_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DAT(3).LFBK));
PORTA(3) <= PORTA_I(3) when PORTA_OE(3) = '1' else 'Z';
PORTA_OE(3) <= XLXI_85/DIR(3).LFBK;
FTCPE_PORTA4: FTCPE port map (PORTA_I(4),PORTA_T(4),DIOWn,NOT RESETn,'0');
PORTA_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_85/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_85/DAT(4).LFBK));
PORTA(4) <= PORTA_I(4) when PORTA_OE(4) = '1' else 'Z';
PORTA_OE(4) <= XLXI_85/DIR(4).LFBK;
FTCPE_PORTA5: FTCPE port map (PORTA_I(5),PORTA_T(5),DIOWn,NOT RESETn,'0');
PORTA_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DAT(5).LFBK));
PORTA(5) <= PORTA_I(5) when PORTA_OE(5) = '1' else 'Z';
PORTA_OE(5) <= XLXI_85/DIR(5);
FTCPE_PORTA6: FTCPE port map (PORTA_I(6),PORTA_T(6),DIOWn,NOT RESETn,'0');
PORTA_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DAT(6).LFBK));
PORTA(6) <= PORTA_I(6) when PORTA_OE(6) = '1' else 'Z';
PORTA_OE(6) <= XLXI_85/DIR(6).LFBK;
FTCPE_PORTA7: FTCPE port map (PORTA_I(7),PORTA_T(7),DIOWn,NOT RESETn,'0');
PORTA_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DAT(7).LFBK));
PORTA(7) <= PORTA_I(7) when PORTA_OE(7) = '1' else 'Z';
PORTA_OE(7) <= XLXI_85/DIR(7);
FTCPE_PORTB0: FTCPE port map (PORTB_I(0),PORTB_T(0),DIOWn,NOT RESETn,'0');
PORTB_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DAT(0).LFBK));
PORTB(0) <= PORTB_I(0) when PORTB_OE(0) = '1' else 'Z';
PORTB_OE(0) <= XLXI_82/DIR(0).LFBK;
FTCPE_PORTB1: FTCPE port map (PORTB_I(1),PORTB_T(1),DIOWn,NOT RESETn,'0');
PORTB_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DAT(1).LFBK));
PORTB(1) <= PORTB_I(1) when PORTB_OE(1) = '1' else 'Z';
PORTB_OE(1) <= XLXI_82/DIR(1).LFBK;
FTCPE_PORTB2: FTCPE port map (PORTB_I(2),PORTB_T(2),DIOWn,NOT RESETn,'0');
PORTB_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH1n AND DH2n AND
DH3n AND CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
NOT XLXI_82/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH1n AND DH2n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_447.LFBK AND
XLXI_82/DAT(2).LFBK));
PORTB(2) <= PORTB_I(2) when PORTB_OE(2) = '1' else 'Z';
PORTB_OE(2) <= XLXI_82/DIR(2);
FTCPE_PORTB3: FTCPE port map (PORTB_I(3),PORTB_T(3),DIOWn,NOT RESETn,'0');
PORTB_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DAT(3).LFBK));
PORTB(3) <= PORTB_I(3) when PORTB_OE(3) = '1' else 'Z';
PORTB_OE(3) <= XLXI_82/DIR(3);
FTCPE_PORTB4: FTCPE port map (PORTB_I(4),PORTB_T(4),DIOWn,NOT RESETn,'0');
PORTB_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(4).LFBK));
PORTB(4) <= PORTB_I(4) when PORTB_OE(4) = '1' else 'Z';
PORTB_OE(4) <= XLXI_82/DIR(4).LFBK;
FTCPE_PORTB5: FTCPE port map (PORTB_I(5),PORTB_T(5),DIOWn,NOT RESETn,'0');
PORTB_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DAT(5).LFBK));
PORTB(5) <= PORTB_I(5) when PORTB_OE(5) = '1' else 'Z';
PORTB_OE(5) <= XLXI_82/DIR(5).LFBK;
FTCPE_PORTB6: FTCPE port map (PORTB_I(6),PORTB_T(6),DIOWn,NOT RESETn,'0');
PORTB_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DAT(6).LFBK));
PORTB(6) <= PORTB_I(6) when PORTB_OE(6) = '1' else 'Z';
PORTB_OE(6) <= XLXI_82/DIR(6).LFBK;
FTCPE_PORTB7: FTCPE port map (PORTB_I(7),PORTB_T(7),DIOWn,NOT RESETn,'0');
PORTB_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DAT(7).LFBK));
PORTB(7) <= PORTB_I(7) when PORTB_OE(7) = '1' else 'Z';
PORTB_OE(7) <= XLXI_82/DIR(7).LFBK;
FTCPE_PORTC0: FTCPE port map (PORTC_I(0),PORTC_T(0),DIOWn,NOT RESETn,'0');
PORTC_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(0).LFBK));
PORTC(0) <= PORTC_I(0) when PORTC_OE(0) = '1' else 'Z';
PORTC_OE(0) <= XLXI_87/DIR(0).LFBK;
FTCPE_PORTC1: FTCPE port map (PORTC_I(1),PORTC_T(1),DIOWn,NOT RESETn,'0');
PORTC_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(1).LFBK));
PORTC(1) <= PORTC_I(1) when PORTC_OE(1) = '1' else 'Z';
PORTC_OE(1) <= XLXI_87/DIR(1).LFBK;
FTCPE_PORTC2: FTCPE port map (PORTC_I(2),PORTC_T(2),DIOWn,NOT RESETn,'0');
PORTC_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DAT(2).LFBK));
PORTC(2) <= PORTC_I(2) when PORTC_OE(2) = '1' else 'Z';
PORTC_OE(2) <= XLXI_87/DIR(2).LFBK;
FTCPE_PORTC3: FTCPE port map (PORTC_I(3),PORTC_T(3),DIOWn,NOT RESETn,'0');
PORTC_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DAT(3).LFBK));
PORTC(3) <= PORTC_I(3) when PORTC_OE(3) = '1' else 'Z';
PORTC_OE(3) <= XLXI_87/DIR(3).LFBK;
FTCPE_PORTC4: FTCPE port map (PORTC_I(4),PORTC_T(4),DIOWn,NOT RESETn,'0');
PORTC_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_87/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_87/DAT(4).LFBK));
PORTC(4) <= PORTC_I(4) when PORTC_OE(4) = '1' else 'Z';
PORTC_OE(4) <= XLXI_87/DIR(4).LFBK;
FTCPE_PORTC5: FTCPE port map (PORTC_I(5),PORTC_T(5),DIOWn,NOT RESETn,'0');
PORTC_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(5).LFBK));
PORTC(5) <= PORTC_I(5) when PORTC_OE(5) = '1' else 'Z';
PORTC_OE(5) <= XLXI_87/DIR(5).LFBK;
FTCPE_PORTC6: FTCPE port map (PORTC_I(6),PORTC_T(6),DIOWn,NOT RESETn,'0');
PORTC_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(6).LFBK));
PORTC(6) <= PORTC_I(6) when PORTC_OE(6) = '1' else 'Z';
PORTC_OE(6) <= XLXI_87/DIR(6).LFBK;
FTCPE_PORTC7: FTCPE port map (PORTC_I(7),PORTC_T(7),DIOWn,NOT RESETn,'0');
PORTC_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DAT(7).LFBK));
PORTC(7) <= PORTC_I(7) when PORTC_OE(7) = '1' else 'Z';
PORTC_OE(7) <= XLXI_87/DIR(7).LFBK;
FTCPE_PORTD0: FTCPE port map (PORTD_I(0),PORTD_T(0),DIOWn,NOT RESETn,'0');
PORTD_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(0).LFBK));
PORTD(0) <= PORTD_I(0) when PORTD_OE(0) = '1' else 'Z';
PORTD_OE(0) <= XLXI_86/DIR(0).LFBK;
FTCPE_PORTD1: FTCPE port map (PORTD_I(1),PORTD_T(1),DIOWn,NOT RESETn,'0');
PORTD_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(1).LFBK));
PORTD(1) <= PORTD_I(1) when PORTD_OE(1) = '1' else 'Z';
PORTD_OE(1) <= XLXI_86/DIR(1).LFBK;
FTCPE_PORTD2: FTCPE port map (PORTD_I(2),PORTD_T(2),DIOWn,NOT RESETn,'0');
PORTD_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DAT(2).LFBK));
PORTD(2) <= PORTD_I(2) when PORTD_OE(2) = '1' else 'Z';
PORTD_OE(2) <= XLXI_86/DIR(2).LFBK;
FTCPE_PORTD3: FTCPE port map (PORTD_I(3),PORTD_T(3),DIOWn,NOT RESETn,'0');
PORTD_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DAT(3).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DAT(3).LFBK));
PORTD(3) <= PORTD_I(3) when PORTD_OE(3) = '1' else 'Z';
PORTD_OE(3) <= XLXI_86/DIR(3).LFBK;
FTCPE_PORTD4: FTCPE port map (PORTD_I(4),PORTD_T(4),DIOWn,NOT RESETn,'0');
PORTD_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_86/DAT(4).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_86/DAT(4).LFBK));
PORTD(4) <= PORTD_I(4) when PORTD_OE(4) = '1' else 'Z';
PORTD_OE(4) <= XLXI_86/DIR(4).LFBK;
FTCPE_PORTD5: FTCPE port map (PORTD_I(5),PORTD_T(5),DIOWn,NOT RESETn,'0');
PORTD_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(5).LFBK));
PORTD(5) <= PORTD_I(5) when PORTD_OE(5) = '1' else 'Z';
PORTD_OE(5) <= XLXI_86/DIR(5).LFBK;
FTCPE_PORTD6: FTCPE port map (PORTD_I(6),PORTD_T(6),DIOWn,NOT RESETn,'0');
PORTD_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(6).LFBK));
PORTD(6) <= PORTD_I(6) when PORTD_OE(6) = '1' else 'Z';
PORTD_OE(6) <= XLXI_86/DIR(6).LFBK;
FTCPE_PORTD7: FTCPE port map (PORTD_I(7),PORTD_T(7),DIOWn,NOT RESETn,'0');
PORTD_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DAT(7).LFBK));
PORTD(7) <= PORTD_I(7) when PORTD_OE(7) = '1' else 'Z';
PORTD_OE(7) <= XLXI_86/DIR(7).LFBK;
FTCPE_PORTE0: FTCPE port map (PORTE_I(0),PORTE_T(0),DIOWn,NOT RESETn,'0');
PORTE_T(0) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DAT(0).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DAT(0).LFBK));
PORTE(0) <= PORTE_I(0) when PORTE_OE(0) = '1' else 'Z';
PORTE_OE(0) <= XLXI_80/DIR(0).LFBK;
FTCPE_PORTE1: FTCPE port map (PORTE_I(1),PORTE_T(1),DIOWn,NOT RESETn,'0');
PORTE_T(1) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DAT(1).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DAT(1).LFBK));
PORTE(1) <= PORTE_I(1) when PORTE_OE(1) = '1' else 'Z';
PORTE_OE(1) <= XLXI_80/DIR(1).LFBK;
FTCPE_PORTE2: FTCPE port map (PORTE_I(2),PORTE_T(2),DIOWn,NOT RESETn,'0');
PORTE_T(2) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH1n AND NOT DH2n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
NOT XLXI_80/DAT(2).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH1n AND NOT DH2n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_447.LFBK AND
XLXI_80/DAT(2).LFBK));
PORTE(2) <= PORTE_I(2) when PORTE_OE(2) = '1' else 'Z';
PORTE_OE(2) <= XLXI_80/DIR(2);
FTCPE_PORTE3: FTCPE port map (PORTE_I(3),PORTE_T(3),DIOWn,NOT RESETn,'0');
PORTE_T(3) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_80/DAT(3).LFBK AND
NOT XLXI_178/XLXN_449.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_80/DAT(3).LFBK AND
NOT XLXI_178/XLXN_449.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_80/DAT(3).LFBK AND
NOT XLXI_178/XLXN_449.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_80/DAT(3).LFBK AND
NOT XLXI_178/XLXN_449.LFBK));
PORTE(3) <= PORTE_I(3) when PORTE_OE(3) = '1' else 'Z';
PORTE_OE(3) <= XLXI_80/DIR(3);
FTCPE_PORTE4: FTCPE port map (PORTE_I(4),PORTE_T(4),DIOWn,NOT RESETn,'0');
PORTE_T(4) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
NOT XLXI_80/DAT(4).LFBK AND XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_80/DAT(4).LFBK AND NOT XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_80/DAT(4).LFBK AND XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
XLXI_80/DAT(4).LFBK AND NOT XLXI_178/XLXN_43.LFBK));
PORTE(4) <= PORTE_I(4) when PORTE_OE(4) = '1' else 'Z';
PORTE_OE(4) <= XLXI_80/DIR(4).LFBK;
FTCPE_PORTE5: FTCPE port map (PORTE_I(5),PORTE_T(5),DIOWn,NOT RESETn,'0');
PORTE_T(5) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_80/DAT(5).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_80/DAT(5).LFBK));
PORTE(5) <= PORTE_I(5) when PORTE_OE(5) = '1' else 'Z';
PORTE_OE(5) <= XLXI_80/DIR(5).LFBK;
FTCPE_PORTE6: FTCPE port map (PORTE_I(6),PORTE_T(6),DIOWn,NOT RESETn,'0');
PORTE_T(6) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DAT(6).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DAT(6).LFBK));
PORTE(6) <= PORTE_I(6) when PORTE_OE(6) = '1' else 'Z';
PORTE_OE(6) <= XLXI_80/DIR(6).LFBK;
FTCPE_PORTE7: FTCPE port map (PORTE_I(7),PORTE_T(7),DIOWn,NOT RESETn,'0');
PORTE_T(7) <= ((NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DAT(7).LFBK)
OR (NOT DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DAT(7).LFBK));
PORTE(7) <= PORTE_I(7) when PORTE_OE(7) = '1' else 'Z';
PORTE_OE(7) <= XLXI_80/DIR(7).LFBK;
REO <= NOT (((NOT DMACKn)
OR (NOT CS1n)
OR (DMARQ)
OR (CS0n)
OR (NOT DH3n)
OR (EXP0_.EXP)
OR (EXP1_.EXP)));
SELECTEDn <= XLXI_178/XLXN_43
XOR
SELECTEDn <= CSEL;
FTCPE_XLXI_178/XLXN_43: FTCPE port map (XLXI_178/XLXN_43,XLXI_178/XLXN_43_T,DIOWn,NOT RESETn,'0');
XLXI_178/XLXN_43_T <= ((NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT XLXI_178/XLXN_43.LFBK)
OR (NOT DA0 AND DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND XLXI_178/XLXN_43.LFBK));
FTCPE_XLXI_80/DIR0: FTCPE port map (XLXI_80/DIR(0),XLXI_80/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(0).LFBK));
FTCPE_XLXI_80/DIR1: FTCPE port map (XLXI_80/DIR(1),XLXI_80/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(1).LFBK));
FTCPE_XLXI_80/DIR2: FTCPE port map (XLXI_80/DIR(2),XLXI_80/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(2).LFBK));
FTCPE_XLXI_80/DIR3: FTCPE port map (XLXI_80/DIR(3),XLXI_80/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_80/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_80/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_80/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_80/DIR(3).LFBK));
FTCPE_XLXI_80/DIR4: FTCPE port map (XLXI_80/DIR(4),XLXI_80/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(4).LFBK));
FTCPE_XLXI_80/DIR5: FTCPE port map (XLXI_80/DIR(5),XLXI_80/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_80/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_80/DIR(5).LFBK));
FTCPE_XLXI_80/DIR6: FTCPE port map (XLXI_80/DIR(6),XLXI_80/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(6).LFBK));
FTCPE_XLXI_80/DIR7: FTCPE port map (XLXI_80/DIR(7),XLXI_80/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_80/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_80/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_80/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_80/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_80/DIR(7).LFBK));
FTCPE_XLXI_82/DIR0: FTCPE port map (XLXI_82/DIR(0),XLXI_82/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DIR(0).LFBK));
FTCPE_XLXI_82/DIR1: FTCPE port map (XLXI_82/DIR(1),XLXI_82/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DIR(1).LFBK));
FTCPE_XLXI_82/DIR2: FTCPE port map (XLXI_82/DIR(2),XLXI_82/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_82/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_82/DIR(2).LFBK));
FTCPE_XLXI_82/DIR3: FTCPE port map (XLXI_82/DIR(3),XLXI_82/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_82/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_82/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_82/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_82/DIR(3).LFBK));
FTCPE_XLXI_82/DIR4: FTCPE port map (XLXI_82/DIR(4),XLXI_82/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(4).LFBK));
FTCPE_XLXI_82/DIR5: FTCPE port map (XLXI_82/DIR(5),XLXI_82/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_82/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_82/DIR(5).LFBK));
FTCPE_XLXI_82/DIR6: FTCPE port map (XLXI_82/DIR(6),XLXI_82/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DIR(6).LFBK));
FTCPE_XLXI_82/DIR7: FTCPE port map (XLXI_82/DIR(7),XLXI_82/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_82/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_82/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_82/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_82/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_82/DIR(7).LFBK));
FTCPE_XLXI_85/DIR0: FTCPE port map (XLXI_85/DIR(0),XLXI_85/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DIR(0).LFBK));
FTCPE_XLXI_85/DIR1: FTCPE port map (XLXI_85/DIR(1),XLXI_85/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DIR(1).LFBK));
FTCPE_XLXI_85/DIR2: FTCPE port map (XLXI_85/DIR(2),XLXI_85/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_85/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_85/DIR(2).LFBK));
FTCPE_XLXI_85/DIR3: FTCPE port map (XLXI_85/DIR(3),XLXI_85/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_85/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_85/DIR(3).LFBK));
FTCPE_XLXI_85/DIR4: FTCPE port map (XLXI_85/DIR(4),XLXI_85/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_85/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_85/DIR(4).LFBK));
FTCPE_XLXI_85/DIR5: FTCPE port map (XLXI_85/DIR(5),XLXI_85/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(5).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_85/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_85/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(5).PIN AND NOT DH0n AND DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_85/DIR(5).LFBK));
FTCPE_XLXI_85/DIR6: FTCPE port map (XLXI_85/DIR(6),XLXI_85/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DIR(6).LFBK));
FTCPE_XLXI_85/DIR7: FTCPE port map (XLXI_85/DIR(7),XLXI_85/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_85/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_85/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_85/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_85/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_85/DIR(7).LFBK));
FTCPE_XLXI_86/DIR0: FTCPE port map (XLXI_86/DIR(0),XLXI_86/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(0).LFBK));
FTCPE_XLXI_86/DIR1: FTCPE port map (XLXI_86/DIR(1),XLXI_86/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(1).LFBK));
FTCPE_XLXI_86/DIR2: FTCPE port map (XLXI_86/DIR(2),XLXI_86/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
NOT XLXI_86/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND DH0n AND DH1n AND
DH3n AND NOT CSEL AND NOT XLXI_178/XLXN_449.LFBK AND
XLXI_86/DIR(2).LFBK));
FTCPE_XLXI_86/DIR3: FTCPE port map (XLXI_86/DIR(3),XLXI_86/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_86/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND DH0n AND NOT DH2n AND
NOT CSEL AND XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_86/DIR(3).LFBK));
FTCPE_XLXI_86/DIR4: FTCPE port map (XLXI_86/DIR(4),XLXI_86/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_86/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_86/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND DH0n AND DH1n AND NOT DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_86/DIR(4).LFBK));
FTCPE_XLXI_86/DIR5: FTCPE port map (XLXI_86/DIR(5),XLXI_86/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(5).LFBK));
FTCPE_XLXI_86/DIR6: FTCPE port map (XLXI_86/DIR(6),XLXI_86/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(6).LFBK));
FTCPE_XLXI_86/DIR7: FTCPE port map (XLXI_86/DIR(7),XLXI_86/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_86/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND NOT XLXI_86/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND CSEL AND XLXI_86/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND NOT XLXI_86/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND DH0n AND DH1n AND
NOT DH2n AND DH3n AND NOT CSEL AND XLXI_86/DIR(7).LFBK));
FTCPE_XLXI_87/DIR0: FTCPE port map (XLXI_87/DIR(0),XLXI_87/DIR_T(0),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(0) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(0).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(0).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(0).LFBK));
FTCPE_XLXI_87/DIR1: FTCPE port map (XLXI_87/DIR(1),XLXI_87/DIR_T(1),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(1) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(1).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(1).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(1).LFBK));
FTCPE_XLXI_87/DIR2: FTCPE port map (XLXI_87/DIR(2),XLXI_87/DIR_T(2),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(2) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
NOT XLXI_87/DIR(2).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(2).PIN AND NOT DH0n AND NOT DH1n AND
DH3n AND NOT CSEL AND XLXI_178/XLXN_449.LFBK AND
XLXI_87/DIR(2).LFBK));
FTCPE_XLXI_87/DIR3: FTCPE port map (XLXI_87/DIR(3),XLXI_87/DIR_T(3),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(3) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
NOT XLXI_87/DIR(3).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(3).PIN AND NOT DH0n AND DH2n AND
NOT CSEL AND NOT XLXI_178/XLXN_448.LFBK AND XLXI_178/XLXN_450.LFBK AND
XLXI_87/DIR(3).LFBK));
FTCPE_XLXI_87/DIR4: FTCPE port map (XLXI_87/DIR(4),XLXI_87/DIR_T(4),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(4) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND NOT XLXI_87/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND CSEL AND
XLXI_178/XLXN_43.LFBK AND XLXI_87/DIR(4).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT DD(4).PIN AND NOT DH0n AND NOT DH1n AND DH2n AND DH3n AND NOT CSEL AND
NOT XLXI_178/XLXN_43.LFBK AND XLXI_87/DIR(4).LFBK));
FTCPE_XLXI_87/DIR5: FTCPE port map (XLXI_87/DIR(5),XLXI_87/DIR_T(5),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(5) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(5).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(5).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(5).LFBK));
FTCPE_XLXI_87/DIR6: FTCPE port map (XLXI_87/DIR(6),XLXI_87/DIR_T(6),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(6) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(6).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(6).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(6).LFBK));
FTCPE_XLXI_87/DIR7: FTCPE port map (XLXI_87/DIR(7),XLXI_87/DIR_T(7),DIOWn,NOT RESETn,'0');
XLXI_87/DIR_T(7) <= ((DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND NOT XLXI_87/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND CSEL AND XLXI_87/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND NOT XLXI_87/DIR(7).LFBK)
OR (DA0 AND NOT DA1 AND DA2 AND DMACKn AND CS1n AND NOT DMARQ AND
NOT CS0n AND NOT XLXI_178/XLXN_43 AND NOT DD(7).PIN AND NOT DH0n AND NOT DH1n AND
DH2n AND DH3n AND NOT CSEL AND XLXI_87/DIR(7).LFBK));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144-10-PQ100
----------------------------------------
/100 98 96 94 92 90 88 86 84 82 \
| 99 97 95 93 91 89 87 85 83 81 |
| 1 80 |
| 2 79 |
| 3 78 |
| 4 77 |
| 5 76 |
| 6 75 |
| 7 74 |
| 8 73 |
| 9 72 |
| 10 71 |
| 11 70 |
| 12 69 |
| 13 XC95144-10-PQ100 68 |
| 14 67 |
| 15 66 |
| 16 65 |
| 17 64 |
| 18 63 |
| 19 62 |
| 20 61 |
| 21 60 |
| 22 59 |
| 23 58 |
| 24 57 |
| 25 56 |
| 26 55 |
| 27 54 |
| 28 53 |
| 29 52 |
| 30 51 |
| 32 34 36 38 40 42 44 46 48 50 |
\31 33 35 37 39 41 43 45 47 49 /
----------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 RESETn 51 PGND
2 GND 52 DD<0>
3 REI 53 VCC
4 PORTB<3> 54 DMARQ
5 PORTA<2> 55 DD<1>
6 PGND 56 PGND
7 VCC 57 DD<2>
8 PORTD<2> 58 DMACKn
9 PORTC<2> 59 VCC
10 DH2n 60 DD<3>
11 PORTE<3> 61 PGND
12 PGND 62 DD<4>
13 PORTE<0> 63 SELECTEDn
14 PORTE<1> 64 GND
15 PORTB<0> 65 DD<5>
16 PORTB<1> 66 DA1
17 PORTA<0> 67 DD<6>
18 PORTD<0> 68 PGND
19 PORTC<0> 69 DD<7>
20 PGND 70 CS1n
21 PGND 71 GND
22 PGND 72 PORTE<2>
23 GND 73 PGND
24 DIOWn 74 PORTB<2>
25 DIORn 75 DH0n
26 PORTE<4> 76 REO
27 PORTE<5> 77 GND
28 VCC 78 PORTA<5>
29 PGND 79 PORTA<7>
30 PORTB<4> 80 CS0n
31 PORTB<5> 81 PORTD<5>
32 PORTA<4> 82 PORTD<7>
33 GND 83 PORTC<5>
34 PORTD<4> 84 PGND
35 PORTC<4> 85 TDO
36 PGND 86 GND
37 PORTA<1> 87 PORTC<7>
38 PORTA<3> 88 PGND
39 PORTD<1> 89 PORTE<6>
40 VCC 90 VCC
41 PORTD<3> 91 PORTE<7>
42 PORTC<1> 92 PORTB<6>
43 PORTC<3> 93 CSEL
44 DH1n 94 PORTB<7>
45 DH3n 95 PORTA<6>
46 GND 96 PORTD<6>
47 TDI 97 DA2
48 PGND 98 PORTC<6>
49 TMS 99 DA0
50 TCK 100 VCC
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144-10-PQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : STD
Ground on Unused IOs : ON
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25