| Design Name | ata_to_isa_06a |
| Device, Speed (SpeedFile Version) | XC95108, -10 (3.0) |
| Date Created | Fri Oct 06 20:09:54 2006 |
| Created By | Timing Report Generator: version I.27 |
| Copyright | Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. |
| Notes and Warnings |
|---|
| Note: This design contains no timing constraints. |
| Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
| Performance Summary | |
|---|---|
| Min. Clock Period | 16.000 ns. |
| Max. Clock Frequency (fSYSTEM) | 62.500 MHz. |
| Limited by Cycle Time for DIOWn | |
| Clock to Setup (tCYC) | 16.000 ns. |
| Pad to Pad Delay (tPD) | 15.500 ns. |
| Setup to Clock at the Pad (tSU) | 7.000 ns. |
| Clock Pad to Output Pad Delay (tCO) | 27.500 ns. |
| Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
|---|---|---|---|---|
| TS1000 | 0.0 | 0.0 | 0 | 0 |
| TS1001 | 0.0 | 0.0 | 0 | 0 |
| TS1002 | 0.0 | 0.0 | 0 | 0 |
| TS1003 | 0.0 | 0.0 | 0 | 0 |
| TS1004 | 0.0 | 0.0 | 0 | 0 |
| TS1005 | 0.0 | 0.0 | 0 | 0 |
| AUTO_TS_F2F | 0.0 | 17.0 | 262 | 262 |
| AUTO_TS_P2P | 0.0 | 27.5 | 69 | 69 |
| AUTO_TS_P2F | 0.0 | 10.5 | 431 | 431 |
| AUTO_TS_F2P | 0.0 | 22.0 | 63 | 63 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| DH0.Q to DD<0>.D | 0.000 | 17.000 | -17.000 |
| DH0.Q to DD<1>.D | 0.000 | 17.000 | -17.000 |
| DH0.Q to DD<2>.D | 0.000 | 17.000 | -17.000 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| INT_A to INTRQ | 0.000 | 27.500 | -27.500 |
| INT_A to ITRPn | 0.000 | 27.500 | -27.500 |
| INT_B to INTRQ | 0.000 | 27.500 | -27.500 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| CS0n to DD<0>.D | 0.000 | 10.500 | -10.500 |
| CS0n to DD<1>.D | 0.000 | 10.500 | -10.500 |
| CS0n to DD<2>.D | 0.000 | 10.500 | -10.500 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| XLXI_395/XLXN_43.Q to REO | 0.000 | 22.000 | -22.000 |
| ITRP_STA<0>.Q to INTRQ | 0.000 | 21.000 | -21.000 |
| ITRP_STA<0>.Q to ITRPn | 0.000 | 21.000 | -21.000 |
| Clock | fEXT (MHz) | Reason |
|---|---|---|
| INT_D | 83.333 | Limited by Clock Pulse Width for INT_D |
| INT_C | 83.333 | Limited by Clock Pulse Width for INT_C |
| INT_B | 83.333 | Limited by Clock Pulse Width for INT_B |
| INT_A | 83.333 | Limited by Clock Pulse Width for INT_A |
| DIORn | 83.333 | Limited by Clock Pulse Width for DIORn |
| DIOWn | 62.500 | Limited by Cycle Time for DIOWn |
| Source Pad | Setup to clk (edge) | Hold to clk (edge) |
|---|---|---|
| CS0n | 4.000 | 1.500 |
| CS1n | 4.000 | 1.500 |
| CSEL | 4.000 | 1.500 |
| DA0 | 4.000 | 1.500 |
| DA1 | 4.000 | 1.500 |
| DA2 | 4.000 | 1.500 |
| DMACKn | 4.000 | 1.500 |
| DMARQ | 4.000 | 1.500 |
| SD<0> | 4.000 | 0.000 |
| SD<1> | 3.000 | 0.500 |
| SD<2> | 4.000 | 0.000 |
| SD<3> | 3.000 | 0.500 |
| SD<4> | 2.000 | 1.500 |
| SD<5> | 2.000 | 1.500 |
| SD<6> | 2.000 | 1.500 |
| SD<7> | 2.000 | 1.500 |
| Source Pad | Setup to clk (edge) | Hold to clk (edge) |
|---|---|---|
| CS0n | 7.000 | 0.000 |
| CS1n | 7.000 | 0.000 |
| CSEL | 7.000 | 0.000 |
| DA0 | 7.000 | 0.000 |
| DA1 | 7.000 | 0.000 |
| DA2 | 7.000 | 0.000 |
| DD<0> | 7.000 | 0.000 |
| DD<1> | 7.000 | 0.000 |
| DD<2> | 7.000 | 0.000 |
| DD<3> | 7.000 | 0.000 |
| DD<4> | 7.000 | 0.000 |
| DD<5> | 7.000 | 0.000 |
| DD<6> | 7.000 | 0.000 |
| DD<7> | 7.000 | 0.000 |
| DMACKn | 7.000 | 0.000 |
| DMARQ | 7.000 | 0.000 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| INTRQ | 27.500 |
| ITRPn | 27.500 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| INTRQ | 27.500 |
| ITRPn | 27.500 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| INTRQ | 27.500 |
| ITRPn | 27.500 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| INTRQ | 27.500 |
| ITRPn | 27.500 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| DD<0> | 14.500 |
| DD<1> | 14.500 |
| DD<2> | 14.500 |
| DD<3> | 14.500 |
| DD<4> | 14.500 |
| DD<5> | 14.500 |
| DD<6> | 14.500 |
| DD<7> | 14.500 |
| IORn | 14.500 |
| RD_STATEn | 14.500 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| REO | 24.500 |
| IOWn | 23.500 |
| SELECTEDn | 23.500 |
| SD<0> | 19.000 |
| SD<1> | 19.000 |
| SD<2> | 19.000 |
| SD<4> | 19.000 |
| SD<5> | 19.000 |
| SD<6> | 19.000 |
| SD<7> | 19.000 |
| ISA_RESET | 17.500 |
| INTRQ | 13.000 |
| SD<3> | 13.000 |
| AEN | 10.500 |
| SA_HIGH<0> | 10.500 |
| SA_HIGH<1> | 10.500 |
| SA_HIGH<2> | 10.500 |
| SA_HIGH<3> | 10.500 |
| SA_HIGH<4> | 10.500 |
| SA_HIGH<5> | 10.500 |
| SA_HIGH<6> | 10.500 |
| SA_HIGH<7> | 10.500 |
| SA_LOW<0> | 10.500 |
| SA_LOW<1> | 10.500 |
| SA_LOW<2> | 10.500 |
| SA_LOW<3> | 10.500 |
| SA_LOW<4> | 10.500 |
| SA_LOW<5> | 10.500 |
| SA_LOW<6> | 10.500 |
| SA_LOW<7> | 10.500 |
| WR_STATE_1n | 10.500 |
| WR_STATE_2n | 10.500 |
| Source | Destination | Delay |
|---|---|---|
| IORn.Q | IORn.D | 9.000 |
| IORn.Q | RD_STATEn.D | 9.000 |
| Source | Destination | Delay |
|---|---|---|
| DH0.Q | INTE_D.D | 16.000 |
| DH0.Q | SD<3>.D | 16.000 |
| DH0.Q | SD<4>.D | 16.000 |
| DH0.Q | SD<5>.D | 16.000 |
| DH0.Q | SD<6>.D | 16.000 |
| DH1.Q | INTE_D.D | 16.000 |
| DH1.Q | SD<3>.D | 16.000 |
| DH1.Q | SD<4>.D | 16.000 |
| DH1.Q | SD<5>.D | 16.000 |
| DH1.Q | SD<6>.D | 16.000 |
| DH2.Q | INTE_D.D | 16.000 |
| DH2.Q | SD<3>.D | 16.000 |
| DH2.Q | SD<4>.D | 16.000 |
| DH2.Q | SD<5>.D | 16.000 |
| DH2.Q | SD<6>.D | 16.000 |
| DH3.Q | INTE_D.D | 16.000 |
| DH3.Q | SD<3>.D | 16.000 |
| DH3.Q | SD<4>.D | 16.000 |
| DH3.Q | SD<5>.D | 16.000 |
| DH3.Q | SD<6>.D | 16.000 |
| WR_STATE_1n.Q | SD<0>.D | 16.000 |
| WR_STATE_1n.Q | SD<1>.D | 16.000 |
| WR_STATE_1n.Q | SD<2>.D | 16.000 |
| WR_STATE_1n.Q | SD<4>.D | 16.000 |
| WR_STATE_1n.Q | SD<5>.D | 16.000 |
| WR_STATE_1n.Q | SD<6>.D | 16.000 |
| WR_STATE_1n.Q | SD<7>.D | 16.000 |
| XLXI_395/XLXN_43.Q | INTE_D.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<0>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<1>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<2>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<3>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<4>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<5>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<6>.D | 16.000 |
| XLXI_395/XLXN_43.Q | SD<7>.D | 16.000 |
| DH0.Q | AEN.D | 15.000 |
| DH0.Q | GATE_ITRP.D | 15.000 |
| DH0.Q | RESET_CTL.D | 15.000 |
| DH0.Q | SA_HIGH<0>.D | 15.000 |
| DH0.Q | SA_HIGH<1>.D | 15.000 |
| DH0.Q | SA_HIGH<3>.D | 15.000 |
| DH0.Q | SA_HIGH<4>.D | 15.000 |
| DH0.Q | SA_HIGH<5>.D | 15.000 |
| DH0.Q | SA_HIGH<6>.D | 15.000 |
| DH0.Q | SA_HIGH<7>.D | 15.000 |
| DH0.Q | SA_LOW<0>.D | 15.000 |
| DH0.Q | SA_LOW<1>.D | 15.000 |
| DH0.Q | SA_LOW<2>.D | 15.000 |
| DH0.Q | SA_LOW<4>.D | 15.000 |
| DH0.Q | SA_LOW<5>.D | 15.000 |
| DH0.Q | SA_LOW<6>.D | 15.000 |
| DH0.Q | SA_LOW<7>.D | 15.000 |
| DH0.Q | WR_STATE_1n.D | 15.000 |
| DH1.Q | AEN.D | 15.000 |
| DH1.Q | GATE_ITRP.D | 15.000 |
| DH1.Q | RESET_CTL.D | 15.000 |
| DH1.Q | SA_HIGH<0>.D | 15.000 |
| DH1.Q | SA_HIGH<1>.D | 15.000 |
| DH1.Q | SA_HIGH<3>.D | 15.000 |
| DH1.Q | SA_HIGH<4>.D | 15.000 |
| DH1.Q | SA_HIGH<5>.D | 15.000 |
| DH1.Q | SA_HIGH<6>.D | 15.000 |
| DH1.Q | SA_HIGH<7>.D | 15.000 |
| DH1.Q | SA_LOW<0>.D | 15.000 |
| DH1.Q | SA_LOW<1>.D | 15.000 |
| DH1.Q | SA_LOW<2>.D | 15.000 |
| DH1.Q | SA_LOW<4>.D | 15.000 |
| DH1.Q | SA_LOW<5>.D | 15.000 |
| DH1.Q | SA_LOW<6>.D | 15.000 |
| DH1.Q | SA_LOW<7>.D | 15.000 |
| DH1.Q | WR_STATE_1n.D | 15.000 |
| DH2.Q | AEN.D | 15.000 |
| DH2.Q | GATE_ITRP.D | 15.000 |
| DH2.Q | RESET_CTL.D | 15.000 |
| DH2.Q | SA_HIGH<0>.D | 15.000 |
| DH2.Q | SA_HIGH<1>.D | 15.000 |
| DH2.Q | SA_HIGH<3>.D | 15.000 |
| DH2.Q | SA_HIGH<4>.D | 15.000 |
| DH2.Q | SA_HIGH<5>.D | 15.000 |
| DH2.Q | SA_HIGH<6>.D | 15.000 |
| DH2.Q | SA_HIGH<7>.D | 15.000 |
| DH2.Q | SA_LOW<0>.D | 15.000 |
| DH2.Q | SA_LOW<1>.D | 15.000 |
| DH2.Q | SA_LOW<2>.D | 15.000 |
| DH2.Q | SA_LOW<4>.D | 15.000 |
| DH2.Q | SA_LOW<5>.D | 15.000 |
| DH2.Q | SA_LOW<6>.D | 15.000 |
| DH2.Q | SA_LOW<7>.D | 15.000 |
| DH2.Q | WR_STATE_1n.D | 15.000 |
| DH3.Q | AEN.D | 15.000 |
| DH3.Q | GATE_ITRP.D | 15.000 |
| DH3.Q | RESET_CTL.D | 15.000 |
| DH3.Q | SA_HIGH<0>.D | 15.000 |
| DH3.Q | SA_HIGH<1>.D | 15.000 |
| DH3.Q | SA_HIGH<3>.D | 15.000 |
| DH3.Q | SA_HIGH<4>.D | 15.000 |
| DH3.Q | SA_HIGH<5>.D | 15.000 |
| DH3.Q | SA_HIGH<6>.D | 15.000 |
| DH3.Q | SA_HIGH<7>.D | 15.000 |
| DH3.Q | SA_LOW<0>.D | 15.000 |
| DH3.Q | SA_LOW<1>.D | 15.000 |
| DH3.Q | SA_LOW<2>.D | 15.000 |
| DH3.Q | SA_LOW<4>.D | 15.000 |
| DH3.Q | SA_LOW<5>.D | 15.000 |
| DH3.Q | SA_LOW<6>.D | 15.000 |
| DH3.Q | SA_LOW<7>.D | 15.000 |
| DH3.Q | WR_STATE_1n.D | 15.000 |
| XLXI_395/XLXN_43.Q | AEN.D | 15.000 |
| XLXI_395/XLXN_43.Q | INTE_A.D | 15.000 |
| XLXI_395/XLXN_43.Q | INTE_B.D | 15.000 |
| XLXI_395/XLXN_43.Q | INTE_C.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<0>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<1>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<2>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<3>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<4>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<5>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<6>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_HIGH<7>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<0>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<1>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<2>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<3>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<4>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<5>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<6>.D | 15.000 |
| XLXI_395/XLXN_43.Q | SA_LOW<7>.D | 15.000 |
| XLXI_395/XLXN_43.Q | WR_STATE_1n.D | 15.000 |
| DH0.Q | SD<0>.D | 10.000 |
| DH0.Q | SD<1>.D | 10.000 |
| DH0.Q | SD<2>.D | 10.000 |
| DH0.Q | SD<7>.D | 10.000 |
| DH1.Q | SD<0>.D | 10.000 |
| DH1.Q | SD<1>.D | 10.000 |
| DH1.Q | SD<2>.D | 10.000 |
| DH1.Q | SD<7>.D | 10.000 |
| DH2.Q | SD<0>.D | 10.000 |
| DH2.Q | SD<1>.D | 10.000 |
| DH2.Q | SD<2>.D | 10.000 |
| DH2.Q | SD<7>.D | 10.000 |
| DH3.Q | SD<0>.D | 10.000 |
| DH3.Q | SD<1>.D | 10.000 |
| DH3.Q | SD<2>.D | 10.000 |
| DH3.Q | SD<7>.D | 10.000 |
| INTE_D.Q | INTE_D.D | 10.000 |
| SD<0>.Q | SD<0>.D | 10.000 |
| SD<1>.Q | SD<1>.D | 10.000 |
| SD<2>.Q | SD<2>.D | 10.000 |
| SD<3>.Q | SD<3>.D | 10.000 |
| SD<4>.Q | SD<4>.D | 10.000 |
| SD<5>.Q | SD<5>.D | 10.000 |
| SD<6>.Q | SD<6>.D | 10.000 |
| SD<7>.Q | SD<7>.D | 10.000 |
| WR_STATE_1n.Q | SD<3>.D | 10.000 |
| AEN.Q | AEN.D | 9.000 |
| DH0.Q | DH0.D | 9.000 |
| DH0.Q | INTE_A.D | 9.000 |
| DH0.Q | INTE_B.D | 9.000 |
| DH0.Q | INTE_C.D | 9.000 |
| DH0.Q | SA_HIGH<2>.D | 9.000 |
| DH0.Q | SA_LOW<3>.D | 9.000 |
| DH1.Q | DH1.D | 9.000 |
| DH1.Q | INTE_A.D | 9.000 |
| DH1.Q | INTE_B.D | 9.000 |
| DH1.Q | INTE_C.D | 9.000 |
| DH1.Q | SA_HIGH<2>.D | 9.000 |
| DH1.Q | SA_LOW<3>.D | 9.000 |
| DH2.Q | DH2.D | 9.000 |
| DH2.Q | INTE_A.D | 9.000 |
| DH2.Q | INTE_B.D | 9.000 |
| DH2.Q | INTE_C.D | 9.000 |
| DH2.Q | SA_HIGH<2>.D | 9.000 |
| DH2.Q | SA_LOW<3>.D | 9.000 |
| DH3.Q | DH3.D | 9.000 |
| DH3.Q | INTE_A.D | 9.000 |
| DH3.Q | INTE_B.D | 9.000 |
| DH3.Q | INTE_C.D | 9.000 |
| DH3.Q | SA_HIGH<2>.D | 9.000 |
| DH3.Q | SA_LOW<3>.D | 9.000 |
| GATE_ITRP.Q | GATE_ITRP.D | 9.000 |
| INTE_A.Q | INTE_A.D | 9.000 |
| INTE_B.Q | INTE_B.D | 9.000 |
| INTE_C.Q | INTE_C.D | 9.000 |
| RESET_CTL.Q | RESET_CTL.D | 9.000 |
| SA_HIGH<0>.Q | SA_HIGH<0>.D | 9.000 |
| SA_HIGH<1>.Q | SA_HIGH<1>.D | 9.000 |
| SA_HIGH<2>.Q | SA_HIGH<2>.D | 9.000 |
| SA_HIGH<3>.Q | SA_HIGH<3>.D | 9.000 |
| SA_HIGH<4>.Q | SA_HIGH<4>.D | 9.000 |
| SA_HIGH<5>.Q | SA_HIGH<5>.D | 9.000 |
| SA_HIGH<6>.Q | SA_HIGH<6>.D | 9.000 |
| SA_HIGH<7>.Q | SA_HIGH<7>.D | 9.000 |
| SA_LOW<0>.Q | SA_LOW<0>.D | 9.000 |
| SA_LOW<1>.Q | SA_LOW<1>.D | 9.000 |
| SA_LOW<2>.Q | SA_LOW<2>.D | 9.000 |
| SA_LOW<3>.Q | SA_LOW<3>.D | 9.000 |
| SA_LOW<4>.Q | SA_LOW<4>.D | 9.000 |
| SA_LOW<5>.Q | SA_LOW<5>.D | 9.000 |
| SA_LOW<6>.Q | SA_LOW<6>.D | 9.000 |
| SA_LOW<7>.Q | SA_LOW<7>.D | 9.000 |
| WR_STATE_1n.Q | WR_STATE_1n.D | 9.000 |
| WR_STATE_1n.Q | WR_STATE_2n.D | 9.000 |
| XLXI_395/XLXN_43.Q | GATE_ITRP.D | 9.000 |
| XLXI_395/XLXN_43.Q | RESET_CTL.D | 9.000 |
| XLXI_395/XLXN_43.Q | XLXI_395/XLXN_43.D | 9.000 |
| Source Pad | Destination Pad | Delay |
|---|---|---|
| CS0n | REO | 15.500 |
| CS1n | REO | 15.500 |
| CSEL | REO | 15.500 |
| DA2 | REO | 15.500 |
| DIORn | REO | 15.500 |
| DMACKn | REO | 15.500 |
| DMARQ | REO | 15.500 |
| CSEL | SELECTEDn | 14.500 |
| DA0 | REO | 14.500 |
| DA1 | REO | 14.500 |
| RESETn | ISA_RESET | 14.500 |
| REI | DD<0> | 6.000 |
| REI | DD<1> | 6.000 |
| REI | DD<2> | 6.000 |
| REI | DD<3> | 6.000 |
| REI | DD<4> | 6.000 |
| REI | DD<5> | 6.000 |
| REI | DD<6> | 6.000 |
| REI | DD<7> | 6.000 |