Timing Report

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Design Name registerbeispiel_01
Device, Speed (SpeedFile Version) XC95108, -7 (3.0)
Date Created Tue Jan 18 16:30:08 2011
Created By Timing Report Generator: version J.33
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 8.000 ns.
Max. Clock Frequency (fSYSTEM) 125.000 MHz.
Limited by Clock Pulse Width for CLK
Clock to Setup (tCYC) 8.000 ns.
Setup to Clock at the Pad (tSU) 4.500 ns.
Clock Pad to Output Pad Delay (tCO) 4.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 8.0 4 4
AUTO_TS_P2P 0.0 4.5 4 4
AUTO_TS_P2F 0.0 6.0 21 21
AUTO_TS_F2P 0.0 3.0 4 4


Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q<0>.Q to Q<0>.D 0.000 8.000 -8.000
Q<1>.Q to Q<1>.D 0.000 8.000 -8.000
Q<2>.Q to Q<2>.D 0.000 8.000 -8.000
Q<3>.Q to Q<3>.D 0.000 8.000 -8.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to Q<0> 0.000 4.500 -4.500
CLK to Q<1> 0.000 4.500 -4.500
CLK to Q<2> 0.000 4.500 -4.500
CLK to Q<3> 0.000 4.500 -4.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLR to Q<0>.D 0.000 6.000 -6.000
CLR to Q<1>.D 0.000 6.000 -6.000
CLR to Q<2>.D 0.000 6.000 -6.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q<0>.Q to Q<0> 0.000 3.000 -3.000
Q<1>.Q to Q<1> 0.000 3.000 -3.000
Q<2>.Q to Q<2> 0.000 3.000 -3.000
Q<3>.Q to Q<3> 0.000 3.000 -3.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 125.000 Limited by Clock Pulse Width for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
CLR 4.500 0.000
D<0> 4.500 0.000
D<1> 4.500 0.000
D<2> 4.500 0.000
D<3> 4.500 0.000
LDN 4.500 0.000
LOAD 4.500 0.000
PRE 4.500 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
Q<0> 4.500
Q<1> 4.500
Q<2> 4.500
Q<3> 4.500


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
Q<0>.Q Q<0>.D 8.000
Q<1>.Q Q<1>.D 8.000
Q<2>.Q Q<2>.D 8.000
Q<3>.Q Q<3>.D 8.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 33
Number of Timing errors: 33
Analysis Completed: Tue Jan 18 16:30:08 2011