cpldfit: version J.33 Xilinx Inc. Fitter Report Design Name: reg_8_2 Date: 1-17-2010, 2:12PM Device Used: XC95108-7-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 8 /108 ( 7%) 39 /540 ( 7%) 64 /216 ( 30%) 8 /108 ( 7%) 21 /69 ( 30%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 2/18 8/36 8 9/90 2/12 FB2 1/18 13/36 13 5/90 1/12 FB3 2/18 13/36 13 10/90 2/12 FB4 1/18 11/36 11 5/90 1/11 FB5 1/18 10/36 10 5/90 1/11 FB6 1/18 9/36 9 5/90 1/11 ----- ----- ----- ----- 8/108 64/216 39/540 8/69 * - Resource is exhausted ** Global Control Resources ** Signal 'C' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 12 12 | I/O : 20 63 Output : 1 1 | GCK/IO : 1 3 Bidirectional : 7 7 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 21 21 ** Power Data ** There are 8 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 8 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D_OUT<1> 5 7 FB1_3 2 I/O I/O STD FAST RESET D_OUT<0> 4 6 FB1_9 6 I/O I/O STD FAST RESET D_OUT<7> 5 13 FB2_3 72 I/O O STD FAST RESET D_OUT<2> 5 8 FB3_3 15 I/O I/O STD FAST RESET D_OUT<6> 5 12 FB3_11 21 I/O I/O STD FAST RESET D_OUT<5> 5 11 FB4_3 58 I/O I/O STD FAST RESET D_OUT<4> 5 10 FB5_3 33 I/O I/O STD FAST RESET D_OUT<3> 5 9 FB6_3 46 I/O I/O STD FAST RESET ** 13 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use D_IN<0> FB1_2 1 I/O I D_IN<7> FB1_8 5 I/O I C FB1_12 9~ GCK/I/O GCK CLR FB2_16 83 I/O I D_IN<5> FB3_2 14 I/O I LD FB3_5 17 I/O I D_IN<1> FB3_16 26 I/O I D_IN<3> FB4_11 66 I/O I D_IN<2> FB4_17 70 I/O I D_IN<6> FB5_9 37 I/O I CTF FB5_17 44 I/O I D_IN<4> FB6_6 48 I/O I CTB FB6_12 53 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 8/28 Number of signals used by logic mapping into function block: 8 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O I D_OUT<1> 5 0 0 0 FB1_3 2 I/O I/O (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 3 I/O (unused) 0 0 0 5 FB1_6 4 I/O (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 5 I/O I D_OUT<0> 4 0 0 1 FB1_9 6 I/O I/O (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 7 I/O (unused) 0 0 0 5 FB1_12 9 GCK/I/O GCK (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 10 GCK/I/O (unused) 0 0 0 5 FB1_15 11 I/O (unused) 0 0 0 5 FB1_16 12 GCK/I/O (unused) 0 0 0 5 FB1_17 13 I/O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: CLR 4: D_IN<0> 7: D_OUT_1.LFBK 2: CTB 5: D_IN<1> 8: LD 3: CTF 6: D_OUT_0.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs D_OUT<1> XXX.XXXX................................ 7 7 D_OUT<0> XXXX.X.X................................ 6 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 13/23 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 71 I/O D_OUT<7> 5 0 0 0 FB2_3 72 I/O O (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 74 GSR/I/O (unused) 0 0 0 5 FB2_6 75 I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 76 GTS/I/O (unused) 0 0 0 5 FB2_9 77 GTS/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 79 I/O (unused) 0 0 0 5 FB2_12 80 I/O (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 81 I/O (unused) 0 0 0 5 FB2_15 82 I/O (unused) 0 0 0 5 FB2_16 83 I/O I (unused) 0 0 0 5 FB2_17 84 I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: CLR 6: D_OUT<1>.PIN 10: D_OUT<5>.PIN 2: CTB 7: D_OUT<2>.PIN 11: D_OUT<6>.PIN 3: CTF 8: D_OUT<3>.PIN 12: D_OUT_7.LFBK 4: D_IN<7> 9: D_OUT<4>.PIN 13: LD 5: D_OUT<0>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs D_OUT<7> XXXXXXXXXXXXX........................... 13 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 13/23 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 14 I/O I D_OUT<2> 5 0 0 0 FB3_3 15 I/O I/O (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 17 I/O I (unused) 0 0 0 5 FB3_6 18 I/O (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 19 I/O (unused) 0 0 0 5 FB3_9 20 I/O (unused) 0 0 0 5 FB3_10 (b) D_OUT<6> 5 0 0 0 FB3_11 21 I/O I/O (unused) 0 0 0 5 FB3_12 23 I/O (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 24 I/O (unused) 0 0 0 5 FB3_15 25 I/O (unused) 0 0 0 5 FB3_16 26 I/O I (unused) 0 0 0 5 FB3_17 31 I/O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: CLR 6: D_OUT<0>.PIN 10: D_OUT<5>.PIN 2: CTB 7: D_OUT<1>.PIN 11: D_OUT_2.LFBK 3: CTF 8: D_OUT<3>.PIN 12: D_OUT_6.LFBK 4: D_IN<2> 9: D_OUT<4>.PIN 13: LD 5: D_IN<6> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs D_OUT<2> XXXX.XX...X.X........................... 8 8 D_OUT<6> XXX.XXXXXXXXX........................... 12 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 11/25 Number of signals used by logic mapping into function block: 11 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 57 I/O D_OUT<5> 5 0 0 0 FB4_3 58 I/O I/O (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 61 I/O (unused) 0 0 0 5 FB4_6 62 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 63 I/O (unused) 0 0 0 5 FB4_9 65 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 66 I/O I (unused) 0 0 0 5 FB4_12 67 I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 68 I/O (unused) 0 0 0 5 FB4_15 69 I/O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 70 I/O I (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: CLR 5: D_OUT<0>.PIN 9: D_OUT<4>.PIN 2: CTB 6: D_OUT<1>.PIN 10: D_OUT_5.LFBK 3: CTF 7: D_OUT<2>.PIN 11: LD 4: D_IN<5> 8: D_OUT<3>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs D_OUT<5> XXXXXXXXXXX............................. 11 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 10/26 Number of signals used by logic mapping into function block: 10 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) (unused) 0 0 0 5 FB5_2 32 I/O D_OUT<4> 5 0 0 0 FB5_3 33 I/O I/O (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 34 I/O (unused) 0 0 0 5 FB5_6 35 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 36 I/O (unused) 0 0 0 5 FB5_9 37 I/O I (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 39 I/O (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 41 I/O (unused) 0 0 0 5 FB5_15 43 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O I (unused) 0 0 0 5 FB5_18 (b) Signals Used by Logic in Function Block 1: CLR 5: D_OUT<0>.PIN 8: D_OUT<3>.PIN 2: CTB 6: D_OUT<1>.PIN 9: D_OUT_4.LFBK 3: CTF 7: D_OUT<2>.PIN 10: LD 4: D_IN<4> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs D_OUT<4> XXXXXXXXXX.............................. 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 9/27 Number of signals used by logic mapping into function block: 9 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 45 I/O D_OUT<3> 5 0 0 0 FB6_3 46 I/O I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 47 I/O (unused) 0 0 0 5 FB6_6 48 I/O I (unused) 0 0 0 5 FB6_7 (b) (unused) 0 0 0 5 FB6_8 50 I/O (unused) 0 0 0 5 FB6_9 51 I/O (unused) 0 0 0 5 FB6_10 (b) (unused) 0 0 0 5 FB6_11 52 I/O (unused) 0 0 0 5 FB6_12 53 I/O I (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 54 I/O (unused) 0 0 0 5 FB6_15 55 I/O (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 56 I/O (unused) 0 0 0 5 FB6_18 (b) Signals Used by Logic in Function Block 1: CLR 4: D_IN<3> 7: D_OUT<2>.PIN 2: CTB 5: D_OUT<0>.PIN 8: D_OUT_3.LFBK 3: CTF 6: D_OUT<1>.PIN 9: LD Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs D_OUT<3> XXXXXXXXX............................... 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_D_OUT0: FDCPE port map (D_OUT(0),D_OUT_D(0),C,'0','0'); D_OUT_D(0) <= ((LD AND NOT CLR AND D_IN(0)) OR (CTF AND NOT LD AND NOT CLR AND NOT D_OUT_0.LFBK) OR (NOT LD AND NOT CLR AND CTB AND NOT D_OUT_0.LFBK) OR (NOT CTF AND NOT LD AND NOT CLR AND NOT CTB AND D_OUT_0.LFBK)); FTCPE_D_OUT1: FTCPE port map (D_OUT(1),D_OUT_T(1),C,'0','0'); D_OUT_T(1) <= ((CLR AND D_OUT_1.LFBK) OR (LD AND NOT D_IN(1) AND D_OUT_1.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT_0.LFBK) OR (LD AND NOT CLR AND D_IN(1) AND NOT D_OUT_1.LFBK) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT_0.LFBK)); FTCPE_D_OUT2: FTCPE port map (D_OUT(2),D_OUT_T(2),C,'0','0'); D_OUT_T(2) <= ((CLR AND D_OUT_2.LFBK) OR (LD AND NOT D_IN(2) AND D_OUT_2.LFBK) OR (LD AND NOT CLR AND D_IN(2) AND NOT D_OUT_2.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN)); FTCPE_D_OUT3: FTCPE port map (D_OUT(3),D_OUT_T(3),C,'0','0'); D_OUT_T(3) <= ((CLR AND D_OUT_3.LFBK) OR (LD AND NOT D_IN(3) AND D_OUT_3.LFBK) OR (LD AND NOT CLR AND D_IN(3) AND NOT D_OUT_3.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND D_OUT(2).PIN) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN AND NOT D_OUT(2).PIN)); FTCPE_D_OUT4: FTCPE port map (D_OUT(4),D_OUT_T(4),C,'0','0'); D_OUT_T(4) <= ((CLR AND D_OUT_4.LFBK) OR (LD AND NOT D_IN(4) AND D_OUT_4.LFBK) OR (LD AND NOT CLR AND D_IN(4) AND NOT D_OUT_4.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND D_OUT(2).PIN AND D_OUT(3).PIN) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN AND NOT D_OUT(2).PIN AND NOT D_OUT(3).PIN)); FTCPE_D_OUT5: FTCPE port map (D_OUT(5),D_OUT_T(5),C,'0','0'); D_OUT_T(5) <= ((CLR AND D_OUT_5.LFBK) OR (LD AND NOT D_IN(5) AND D_OUT_5.LFBK) OR (LD AND NOT CLR AND D_IN(5) AND NOT D_OUT_5.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND D_OUT(2).PIN AND D_OUT(3).PIN AND D_OUT(4).PIN) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN AND NOT D_OUT(2).PIN AND NOT D_OUT(3).PIN AND NOT D_OUT(4).PIN)); FTCPE_D_OUT6: FTCPE port map (D_OUT(6),D_OUT_T(6),C,'0','0'); D_OUT_T(6) <= ((CLR AND D_OUT_6.LFBK) OR (LD AND NOT D_IN(6) AND D_OUT_6.LFBK) OR (LD AND NOT CLR AND D_IN(6) AND NOT D_OUT_6.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT_2.LFBK AND D_OUT(0).PIN AND D_OUT(1).PIN AND D_OUT(3).PIN AND D_OUT(4).PIN AND D_OUT(5).PIN) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT_2.LFBK AND NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN AND NOT D_OUT(3).PIN AND NOT D_OUT(4).PIN AND NOT D_OUT(5).PIN)); FTCPE_D_OUT7: FTCPE port map (D_OUT(7),D_OUT_T(7),C,'0','0'); D_OUT_T(7) <= ((CLR AND D_OUT_7.LFBK) OR (LD AND NOT D_IN(7) AND D_OUT_7.LFBK) OR (LD AND NOT CLR AND D_IN(7) AND NOT D_OUT_7.LFBK) OR (CTF AND NOT LD AND NOT CLR AND D_OUT(0).PIN AND D_OUT(1).PIN AND D_OUT(6).PIN AND D_OUT(2).PIN AND D_OUT(3).PIN AND D_OUT(4).PIN AND D_OUT(5).PIN) OR (NOT CTF AND NOT LD AND NOT CLR AND CTB AND NOT D_OUT(0).PIN AND NOT D_OUT(1).PIN AND NOT D_OUT(6).PIN AND NOT D_OUT(2).PIN AND NOT D_OUT(3).PIN AND NOT D_OUT(4).PIN AND NOT D_OUT(5).PIN)); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-7-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-7-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 D_IN<0> 43 TIE 2 D_OUT<1> 44 CTF 3 TIE 45 TIE 4 TIE 46 D_OUT<3> 5 D_IN<7> 47 TIE 6 D_OUT<0> 48 D_IN<4> 7 TIE 49 GND 8 GND 50 TIE 9 C 51 TIE 10 TIE 52 TIE 11 TIE 53 CTB 12 TIE 54 TIE 13 TIE 55 TIE 14 D_IN<5> 56 TIE 15 D_OUT<2> 57 TIE 16 GND 58 D_OUT<5> 17 LD 59 TDO 18 TIE 60 GND 19 TIE 61 TIE 20 TIE 62 TIE 21 D_OUT<6> 63 TIE 22 VCC 64 VCC 23 TIE 65 TIE 24 TIE 66 D_IN<3> 25 TIE 67 TIE 26 D_IN<1> 68 TIE 27 GND 69 TIE 28 TDI 70 D_IN<2> 29 TMS 71 TIE 30 TCK 72 D_OUT<7> 31 TIE 73 VCC 32 TIE 74 TIE 33 D_OUT<4> 75 TIE 34 TIE 76 TIE 35 TIE 77 TIE 36 TIE 78 VCC 37 D_IN<6> 79 TIE 38 VCC 80 TIE 39 TIE 81 TIE 40 TIE 82 TIE 41 TIE 83 CLR 42 GND 84 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-7-PC84 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25