********** Mapped Logic ********** |
CO <= ((B(3) AND A(3))
OR (B(3) AND Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2) OR (A(3) AND Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2)); |
Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2 <= ((EXP7_.EXP)
OR (A(1) AND B(1))); |
Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2 <= ((EXP0_.EXP)
OR ( Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2.EXP) OR (A(1) AND B(1) AND A(2)) OR (CI AND A(0) AND A(1) AND A(2)) OR (CI AND B(0) AND A(1) AND A(2)) OR (A(0) AND B(0) AND A(1) AND A(2)) OR (A(0) AND B(0) AND B(1) AND A(2))); |
S(0) <= NOT (A(0)
XOR S(0) <= NOT (((CI AND B(0)) OR (NOT CI AND NOT B(0)))); |
S(1) <= NOT (A(1)
XOR S(1) <= NOT (((EXP8_.EXP) OR (EXP9_.EXP) OR (CI AND A(0) AND B(1)) OR (NOT CI AND NOT A(0) AND NOT B(1)) OR (A(0) AND B(0) AND B(1)) OR (NOT A(0) AND NOT B(0) AND NOT B(1)))); |
S(2) <= NOT (A(2)
XOR S(2) <= NOT (((B(2) AND Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2) OR (NOT B(2) AND NOT Madd_AUX_addsub0000__or0001/Madd_AUX_addsub0000__or0001_D2))); |
S(3) <= NOT (A(3)
XOR S(3) <= NOT (((B(3) AND Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2) OR (NOT B(3) AND NOT Madd_AUX_addsub0000__or0002/Madd_AUX_addsub0000__or0002_D2))); |
ZERO <= NOT (((EXP3_.EXP)
OR (EXP4_.EXP) OR (B(3) AND A(3) AND A(1)) OR (NOT B(3) AND NOT A(3) AND A(1)) OR (NOT CI AND NOT B(0) AND NOT A(1) AND B(1)) OR (B(3) AND NOT A(3) AND NOT A(2) AND NOT B(2)) OR (NOT B(3) AND A(3) AND NOT A(2) AND NOT B(2)))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |